# US 7,746,104 B1 · Dynamically controlled output multiplexer circuits in a programmable integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,104 B1 - Document ID: US7746104B1 - Status: Granted - Kind: B1 - Application number: 12/417,024 - Filed: 2009-04-02 - Granted: 2010-06-29 - Earliest claimed: 2009-04-02 - Assignees: Xilinx, Inc. - Inventors: Brian C. Gaide; Steven P. Young - Web page: https://patentgrep.com/patent/US7746104B1 ## CPC - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17736: Structural details of routing resources - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A programmable integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output multiplexer circuit. The output multiplexer circuit includes a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another logic block, and a first data output. A second output multiplexer may also have first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the another logic block, and a second data output. The output multiplexer circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first, second, and select inputs of the circuit. ## Claims ### Claim 1 A programmable integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit; and an output multiplexer circuit comprising a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another of the logic blocks, and a data output coupled to a first output of the logic block, wherein the output multiplexer circuit is programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first data input, the second data input, and the select input of the output multiplexer circuit. ### Claim 2 (depends on 1) The programmable integrated circuit of claim 1, wherein the plurality of logic blocks comprises an array of the logic blocks, and the logic blocks are substantially similar one to another. ### Claim 3 (depends on 2) The programmable integrated circuit of claim 2, wherein for each logic block the select input is coupled to a select output of an output multiplexer circuit in an adjacent logic block in the array. ### Claim 4 (depends on 1) The programmable integrated circuit of claim 1, wherein each output multiplexer circuit further comprises a select multiplexer coupled between the another of the logic blocks and the first multiplexer, the select multiplexer having a first data input coupled to the output of the another of the logic blocks and a data output coupled to the select input of the first multiplexer. ### Claim 5 (depends on 1) The programmable integrated circuit of claim 1, wherein each of the output multiplexer circuits further comprises a second multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to the output of the another of the logic blocks, and a data output coupled to a second output of the logic block. ### Claim 6 (depends on 1) The programmable integrated circuit of claim 1, wherein the first and second data inputs of the output multiplexer circuit and the data output of the output multiplexer circuit each comprise an N-bit bus, N being an integer greater than one. ### Claim 7 A programmable integrated circuit, comprising: a plurality of logic blocks; and an interconnect structure coupled between the logic blocks, wherein each of the logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; and an output multiplexer circuit having first and second data inputs coupled to the first and second outputs of the logic circuit and further having a data output coupled to the interconnect structure, wherein each output multiplexer circuit is programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to output a result of implementing a first multiplexing function between the first and second data inputs; and wherein the first multiplexing function in each output multiplexer circuit is controlled by a select input comprising a dynamic signal. ### Claim 8 (depends on 7) The programmable integrated circuit of claim 7, wherein each output multiplexer circuit is further programmably coupled, in the one of the operating modes, to provide an output token with the result only when the output multiplexer circuit receives tokens indicating valid new data on each of the first data input, the second data input, and the select input. ### Claim 9 (depends on 7) The programmable integrated circuit of claim 7, wherein: the plurality of logic blocks comprises an array of the logic blocks; the logic blocks are substantially similar one to another; and for each logic block the select input is coupled to a select output of an adjacent logic block in the array. ### Claim 10 (depends on 9) The programmable integrated circuit of claim 9, wherein for each logic block the select input is coupled to a select output of an output multiplexer circuit in the adjacent logic block. ### Claim 11 (depends on 7) The programmable integrated circuit of claim 7, wherein each output multiplexer circuit further comprises: a select multiplexer having a first data input coupled to receive the dynamic signal, a second data input, and a data output coupled to control the first multiplexing function. ### Claim 12 (depends on 7) The programmable integrated circuit of claim 7, wherein: each output multiplexer circuit is further programmably coupled, in the one of the operating modes, to output a second value comprising a result of implementing a second multiplexing function between the first and second data inputs; and for each output multiplexer circuit, the second multiplexing function is controlled by the select input. ### Claim 13 (depends on 7) The programmable integrated circuit of claim 7, wherein the first and second data inputs and the output of the output multiplexer circuit each comprise an N-bit bus, N being an integer greater than one, and the dynamic signal on the select input comprises a single-bit value. ### Claim 14 A programmable integrated circuit, comprising: an array of substantially similar programmable logic blocks; and an interconnect structure coupled between the programmable logic blocks, wherein each of the programmable logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; and an output multiplexer circuit having first and second data inputs coupled to the first and second outputs of the logic circuit and further having a data output coupled to the interconnect structure, wherein each output multiplexer circuit is programmably coupled to output a result of implementing a first multiplexing function between the first and second data inputs, and wherein the first multiplexing function in each output multiplexer circuit is controlled by a select input comprising a dynamic signal. ### Claim 15 (depends on 14) The programmable integrated circuit of claim 14, wherein the output multiplexer circuit is programmably coupled to provide an output token with the result only when the output multiplexer circuit receives tokens indicating valid new data on the first data input, the second data input, and the select input. ### Claim 16 (depends on 14) The programmable integrated circuit of claim 14, wherein for each programmable logic block the select input is programmably coupled to a select output of an adjacent programmable logic block in the array. ### Claim 17 (depends on 16) The programmable integrated circuit of claim 16, wherein for each programmable logic block the select input is programmably coupled to a select output of an output multiplexer circuit in the adjacent programmable logic block. ### Claim 18 (depends on 14) The programmable integrated circuit of claim 14, wherein each output multiplexer circuit further comprises: a programmable select multiplexer having a first data input coupled to receive the dynamic signal, a second data input, and a data output coupled to control the first multiplexing function. ### Claim 19 (depends on 14) The programmable integrated circuit of claim 14, wherein each output multiplexer circuit is further programmably coupled to output a second value comprising a result of implementing a second multiplexing function between the first and second data inputs. ### Claim 20 (depends on 14) The programmable integrated circuit of claim 14, wherein the first and second data inputs of the output multiplexer circuit and the data output of the output multiplexer circuit each comprise an N-bit bus, N being an integer greater than one.