# US 7,746,102 B1 · Bus-based logic blocks for self-timed integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,102 B1 - Document ID: US7746102B1 - Status: Granted - Kind: B1 - Application number: 12/417,018 - Filed: 2009-04-02 - Granted: 2010-06-29 - Earliest claimed: 2009-04-02 - Assignees: Xilinx, Inc. - Inventors: Steven P. Young; Brian C. Gaide - Web page: https://patentgrep.com/patent/US7746102B1 ## CPC - H03K 19/17736: Structural details of routing resources - G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A bus-based logic block in a self-timed integrated circuit includes N first input multiplexers, N second input multiplexers, and N lookup tables, N being greater than one. The select inputs of all N first input multiplexers are coupled together, and the select inputs of all N second input multiplexers are coupled together. A corresponding data input of each first input multiplexer is one bit of a first self-timed N-bit bus, and a corresponding data input of each second multiplexer is one bit of a second self-timed N-bit bus. Each lookup table has first and second inputs coupled to the outputs of the first and second input multiplexers. Corresponding control inputs of all N lookup tables are coupled together. Thus, all operations are performed on one or more N-bit self-timed busses, rather than on individual data signals. ## Claims ### Claim 1 A bus-based logic block, comprising: N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another. ### Claim 2 (depends on 1) The bus-based logic block of claim 1, wherein the logic block comprises a programmable logic block arrayed in a programmable integrated circuit. ### Claim 3 (depends on 1) The bus-based logic block of claim 1, further comprising: a first memory cell coupled to the select inputs of all N first input multiplexers; a second memory cell coupled to the select inputs of all N second input multiplexers; and a plurality of third memory cells coupled to the plurality of control inputs of all N first lookup tables, with each of the third memory cells being coupled to a same corresponding control input of each of the N first lookup tables. ### Claim 4 (depends on 1) The bus-based logic block of claim 1, further comprising: N first storage elements each coupled between the output of a corresponding first input multiplexer and the first input of a corresponding first lookup table; N second storage elements each coupled between the output of a corresponding second input multiplexer and the second input of a corresponding first lookup table; and N third storage elements each having a data input coupled to the output of a corresponding first lookup table, wherein: the N first storage elements are commonly controlled one with another; the N second storage elements are commonly controlled one with another; and the N third storage elements are commonly controlled one with another. ### Claim 5 (depends on 1) The bus-based logic block of claim 1, further comprising: an N×N-bit multiply block coupled between the output of the N second input multiplexers and the second input of the N first lookup tables, wherein: a first N-bit input of the multiply block is coupled to the output of the N second input multiplexers; a second N-bit input of the multiply block is coupled to an N-bit input of the logic block; and an N-bit output of the multiply block is coupled to the second inputs of the N first lookup tables, each bit of the N-bit output being coupled to the second input of a corresponding one of the N first lookup tables. ### Claim 6 (depends on 1) The bus-based logic block of claim 1, further comprising: N second lookup tables, each second lookup table having a first input coupled to the output of a corresponding one of the first lookup tables, a second input, a plurality of control inputs, and an output, wherein corresponding control inputs of all N second lookup tables are coupled one to another. ### Claim 7 (depends on 6) The bus-based logic block of claim 6, further comprising: a first memory cell coupled to the select inputs of all N first input multiplexers; a second memory cell coupled to the select inputs of all N second input multiplexers; a plurality of third memory cells coupled to the plurality of control inputs of all N first lookup tables, with each of the third memory cells being coupled to a same corresponding control input of each of the N first lookup tables; and a plurality of fourth memory cells coupled to the plurality of control inputs of all N second lookup tables, with each of the fourth memory cells being coupled to a same corresponding control input of each of the N second lookup tables. ### Claim 8 (depends on 6) The bus-based logic block of claim 6, wherein the outputs of the N second lookup tables comprise corresponding bits of a third self-timed N-bit bus, the third self-timed N-bit bus driving an N-bit output of the logic block. ### Claim 9 An integrated circuit, comprising: an array of logic blocks; and an interconnect structure interconnecting the logic blocks, wherein each logic block comprises: N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus, the first self-timed N-bit bus being coupled to a first N-bit bus of the interconnect structure; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus, the second self-timed N-bit bus being coupled to a second N-bit bus of the interconnect structure; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the integrated circuit comprises a programmable integrated circuit. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the programmable integrated circuit comprises a programmable logic device (PLD). ### Claim 12 (depends on 9) The integrated circuit of claim 9, wherein the logic blocks in the array are all substantially similar. ### Claim 13 (depends on 9) The integrated circuit of claim 9, wherein each logic block further comprises: a first memory cell coupled to the select inputs of all N first input multiplexers; a second memory cell coupled to the select inputs of all N second input multiplexers; and a plurality of third memory cells coupled to the plurality of control inputs of all N first lookup tables, with each of the third memory cells being coupled to a same corresponding control input of each of the N first lookup tables. ### Claim 14 (depends on 9) The integrated circuit of claim 9, wherein each logic block further comprises: N first storage elements each coupled between the output of a corresponding first input multiplexer and the first input of a corresponding first lookup table; N second storage elements each coupled between the output of a corresponding second input multiplexer and the second input of a corresponding first lookup table; and N third storage elements each having a data input coupled to the output of a corresponding first lookup table, wherein: the N first storage elements are commonly controlled one with another; the N second storage elements are commonly controlled one with another; and the N third storage elements are commonly controlled, one with another. ### Claim 15 (depends on 9) The integrated circuit of claim 9, wherein each logic block further comprises: an N×N-bit multiply block coupled between the output of the N second input multiplexers and the second input of the N first lookup tables, wherein: a first N-bit input of the multiply block is coupled to the output of the N second input multiplexers; a second N-bit input of the multiply block is coupled to an N-bit input of the logic block; and an N-bit output of the multiply block is coupled to the second inputs of the N first lookup tables, each bit of the N-bit output being coupled to the second input of a corresponding one of the N first lookup tables. ### Claim 16 (depends on 9) The integrated circuit of claim 9, wherein each logic block further comprises: N second lookup tables, each second lookup table having a first input coupled to the output of a corresponding one of the first lookup tables, a second input, a plurality of control inputs, and an output, wherein corresponding control inputs of all N second lookup tables are coupled one to another. ### Claim 17 (depends on 16) The integrated circuit of claim 16, wherein each logic block further comprises: a first memory cell coupled to the select inputs of all N first input multiplexers; a second memory cell coupled to the select inputs of all N second input multiplexers; a plurality of third memory cells coupled to the plurality of control inputs of all N first lookup tables, with each of the third memory cells being coupled to a same corresponding control input of each of the N first lookup tables; and a plurality of fourth memory cells coupled to the plurality of control inputs of all N second lookup tables, with each of the fourth memory cells being coupled to a same corresponding control input of each of the N second lookup tables. ### Claim 18 (depends on 16) The integrated circuit of claim 16, wherein the outputs of the N second lookup tables comprise corresponding bits of a third self-timed N-bit bus, the third self-timed N-bit bus being coupled to a third N-bit bus of the interconnect structure. ### Claim 19 A programmable integrated circuit, comprising: an array of programmable logic blocks; and an interconnect structure interconnecting the programmable logic blocks, wherein each programmable logic block comprises: N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus, the first self-timed N-bit bus being coupled to a first N-bit bus of the interconnect structure; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus, the second self-timed N-bit bus being coupled to a second N-bit bus of the interconnect structure; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another. ### Claim 20 (depends on 19) The programmable integrated circuit of claim 19, wherein each programmable logic block further comprises: a first programmable memory cell coupled to the select inputs of all N first input multiplexers; a second programmable memory cell coupled to the select inputs of all N second input multiplexers; and a plurality of third programmable memory cells coupled to the plurality of control inputs of all N first lookup tables, each third programmable memory cell being coupled to a same corresponding control input of each of the N first lookup tables.