# US 7,746,099 B1 · Method of and system for implementing a circuit in a device having programmable logic > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,099 B1 - Document ID: US7746099B1 - Status: Granted - Kind: B1 - Application number: 12/008,489 - Filed: 2008-01-11 - Granted: 2010-06-29 - Earliest claimed: 2008-01-11 - Assignees: Xilinx, Inc. - Inventors: Chi Bun Chan; Nabeel Shirazi - Web page: https://patentgrep.com/patent/US7746099B1 ## CPC - H03K 19/17756: for partial configuration or partial reconfiguration - H03K 19/1776: for memories - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed. ## Claims ### Claim 1 A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory, the method comprising: receiving configuration data in configuration memory for implementing a circuit design in the programmable resources; configuring the programmable resources of the device using the configuration data to enable the circuit design; storing data in a block of random access memory of the available internal memory coupled to the circuit design; implementing the circuit design by reading first data from the block of random access memory, wherein implementing the circuit design requires more memory than the predetermined amount of available internal memory; detecting an attempt by the circuit design to read second data which is not stored in the block of random access memory; generating a command to perform a partial reconfiguration of the device in response to detecting the attempt by the circuit design to read the second data which is not stored in the block of random access memory; performing the partial reconfiguration of the device, wherein new data having the second data is stored in the block of random access memory; disabling the implementing the circuit design when performing the partial reconfiguration of the device; and accessing the second data stored in the block of random access memory. ### Claim 2 (depends on 1) The method of claim 1 wherein performing a partial reconfiguration of the device comprises implementing a second circuit design in the programmable resources of the device. ### Claim 3 (depends on 1) The method of claim 1 wherein performing a partial reconfiguration of the device comprises receiving the new data from a memory external to the device having programmable resources. ### Claim 4 (depends on 3) The method of claim 3 wherein receiving the new data from a memory external to the device having programmable resources comprises receiving the new data from a host system by way of a communication interface. ### Claim 5 (depends on 1) The method of claim 1 wherein disabling the implementing the circuit design comprises disabling a clock signal to the circuit design when performing the partial reconfiguration of the device. ### Claim 6 (depends on 1) The method of claim 1 further comprising performing a second partial reconfiguration of the device. ### Claim 7 A system for implementing a circuit in a device having programmable resources, the system comprising: configuration memory storing configuration data for configuring the programmable resources; blocks of random access memory comprising a predetermined amount of available internal memory; a circuit design configured in the programmable resources based upon the configuration data stored in the configuration memory, the circuit design coupled to the blocks of random access memory to access first data stored in the blocks of random access memory, wherein implementing the circuit design requires more memory than the predetermined amount of available internal memory; a communication interface coupled to access data external to the blocks of random access memory; and a memory management unit coupled to the communication interface, the memory management unit generating commands for a partial reconfiguration of the blocks of random access memory after detecting an attempt to read second data which is not stored in the blocks of random access memory, wherein the partial reconfiguration comprises storing the second data in the blocks of random access memory to enable implementing the circuit design using the second data wherein the memory management unit receives an address for accessing the blocks of random access memory from the circuit design configured in the programmable resources; and wherein the implementing the circuit design is disabled during the partial reconfiguration. ### Claim 8 (depends on 7) The system of claim 7 wherein the memory management unit comprises an arbitrator coupled to a plurality of page index registers. ### Claim 9 (depends on 7) The system of claim 7 further comprising a reconfiguration port coupled to the blocks of random access memory for reconfiguring at least a portion of the blocks of random access memory. ### Claim 10 (depends on 7) The system of claim 7 wherein a clock signal is coupled to the circuit design, and wherein the clock signal is disabled when disabling the implementing the circuit design during the partial reconfiguration. ### Claim 11 (depends on 7) The system of claim 7 wherein the system comprises a single integrated circuit device.