# US 7,746,096 B1 · Impedance buffer and method

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- Number: US 7,746,096 B1
- Document ID: US7746096B1
- Status: Granted
- Kind: B1
- Application number: 11/138,823
- Filed: 2005-05-26
- Granted: 2010-06-29
- Earliest claimed: 2004-08-03
- Assignees: Cypress Semiconductor Corporation
- Inventors: Derek Yingqi Yang
- Web page: https://patentgrep.com/patent/US7746096B1

## CPC

- H03K 19/017545: {Coupling arrangements; Impedance matching circuits}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

## Claims

### Claim 1

A method of operating an impedance buffer comprising:
a) comparing a first voltage at a first node between a first pull-up array and a reference resistor to a reference voltage to form a first difference output using a comparator;
b) adjusting an impedance of the first pull-up array based on the first difference output; and
c) comparing a second voltage at a second node between a second pull-up array and a pull-down array to the first voltage at the first node to form a second difference output using the comparator.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
d) adjusting an impedance of the pull-down array based on the second difference output.

### Claim 3 (depends on 1)

The method of claim 1, wherein (a) further comprises:
a1) placing the first pull-up array and the reference resistor in series between a supply voltage and a ground.

### Claim 4 (depends on 1)

The method of claim 1, wherein (a) further comprises:
a1) closing a first switch between the reference voltage and an input of the comparator;
a2) opening a second switch between the input of the comparator and the second node.

### Claim 5 (depends on 4)

The method of claim 4, wherein (a) further comprises:
a3) closing a third switch between an output of the comparator and a pull-up counter/register, wherein the output of the comparator comprises a first difference output;
a4) incrementing or decrementing the pull-up counter/register based on the first difference output of the comparator.

### Claim 6 (depends on 5)

The method of claim 5, wherein (a3) further comprises:
i) opening a fourth switch between the output of the comparator and a pull-down counter/register.

### Claim 7 (depends on 1)

The method of claim 1, wherein (b) further comprises:
b1) repeating the comparing and adjusting steps-until the first difference output is near zero volts;
b2) when the first difference output is near zero volts moving to (c).

### Claim 8 (depends on 1)

The method of claim 1, wherein (c), further comprises:
c1) adjusting an impedance of the second pull-up array to be equal to the impedance of the first pull-up array.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
c2) placing the second pull-up array and the pull-down array in series between a supply voltage and a ground;
c3) closing a second switch between the second node and an input of a comparator; and
c4) opening a first switch between a reference voltage and the input of the comparator.