# US 7,746,046 B2 · Power management unit for use in portable applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,046 B2 - Document ID: US7746046B2 - Status: Granted - Kind: B2 - Application number: 11/790,036 - Filed: 2007-04-23 - Published: 2007-08-23 - Granted: 2010-06-29 - Earliest claimed: 2003-08-20 - Assignees: Broadcom Corporation - Inventors: Chun-Ying Chen - Web page: https://patentgrep.com/patent/US7746046B2 ## CPC - G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) - G05F 1/575: characterised by the feedback circuit - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A voltage regulator includes a first stage capable of receiving a reference voltage and capable of having a first current flowing through the first stage. A second stage is capable of having a second current flowing through the second stage. A third stage is capable of outputting an output voltage and capable of having a third current flowing through the second stage. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load. ## Claims ### Claim 1 A voltage regulator circuit, comprising: a high voltage linear regulator configured to provide an intermediate voltage based upon an input voltage; and a plurality of parallel low voltage regulators coupled to the high voltage linear regulator, each of the plurality of parallel low voltage regulators being configured to provide a corresponding regulated output voltage based upon the intermediate voltage, wherein at least one of the plurality of parallel low voltage regulators comprises: a plurality of stages, each of the stages being configured to include a corresponding current that flows through its respective stage, the corresponding current for each of the stages being proportional to each other, wherein the at least one of the plurality of parallel low voltage regulators is configured to adjust the corresponding current for each of the stages to cause the corresponding regulated output voltage to be proportional to a reference voltage. ### Claim 2 (depends on 1) The voltage regulator circuit of claim 1, wherein each of the plurality of parallel low voltage regulators is configured to receive the intermediate voltage. ### Claim 3 (depends on 1) The voltage regulator circuit of claim 1, wherein the high voltage linear regulator is a low dropout voltage regulator. ### Claim 4 (depends on 1) The voltage regulator circuit of claim 1, wherein at the least one of the plurality of parallel low voltage regulators has a dropout voltage of not more than approximately 14 millivolts for an output current from 0 to 50 mA. ### Claim 5 (depends on 1) The voltage regulator circuit of claim 1, wherein the plurality of stages comprise: a first stage configured to receive the reference voltage and to include a first current flowing through the first stage; a second stage, coupled to the first stage, configured to include a second current flowing through the second stage; and a third stage, coupled to the second stage, configured to output the corresponding regulated output voltage and include a third current flowing through the third stage, wherein the first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and a maximum output current. ### Claim 6 (depends on 5) The voltage regulator circuit of claim 5, wherein the third stage comprises: a pass transistor, wherein the second stage comprises: a first mirror transistor and an input transistor in series with the first mirror transistor, and wherein a gate of the first mirror transistor is driven by a substantially similar voltage as a gate of the pass transistor. ### Claim 7 (depends on 6) The voltage regulator circuit of claim 6, wherein the first stage comprises: a second mirror transistor, wherein a gate of the second mirror transistor is driven by a substantially voltage as the gate of the pass transistor. ### Claim 8 (depends on 7) The voltage regulator circuit of claim 7, further comprising: a low pass filter coupled between the gate of the second mirror transistor and the gate of the first mirror transistor. ### Claim 9 (depends on 8) The voltage regulator circuit of claim 8, wherein the low pass filter comprises: an RC network. ### Claim 10 (depends on 7) The voltage regulator circuit of claim 7, wherein the first stage further comprises: a first trickle current source in parallel with a current source, wherein the current source is parallel with the first mirror transistor. ### Claim 11 (depends on 10) The voltage regulator circuit of claim 10, further comprising: a second trickle current source supplying a trickle current to the second stage. ### Claim 12 (depends on 11) The voltage regulator of claim 11, further comprising: a first shut off transistor in series with the first mirror transistor and the input transistor of the second stage, wherein a gate of the first shut off transistor is configured to receive an output of an opamp, and wherein the opamp is configured to receive the reference voltage at a first input and a voltage from a resistor divider at a second input. ### Claim 13 (depends on 12) The voltage regulator circuit of claim 12, further comprising: a second shut off transistor in series with the second mirror transistor and the input transistor of the first stage, wherein a gate of the second shut off transistor is configured to receive an output of an opamp. ### Claim 14 (depends on 12) The voltage regulator circuit of claim 12, further comprising: an NMOS transistor coupled between the first shut off transistor and the input transistor. ### Claim 15 (depends on 5) The voltage regulator circuit of claim 5, further comprising: a feedback stage having a resistor divider coupled between the third stage and the first stage, wherein a feedback voltage from the resistor divider controls an amplification of the first stage. ### Claim 16 (depends on 1) The voltage regulator circuit of claim 1, wherein the intermediate voltage is substantially less than or equal to a breakdown voltage of the plurality of parallel low voltage regulators and the input voltage is substantially greater than or equal to the breakdown voltage. ### Claim 17 (depends on 1) The voltage regulator circuit of claim 1, further comprising: a multiplexer configured to provide the input voltage by selecting a respective output voltage provided by one of a plurality of power sources. ### Claim 18 (depends on 17) The voltage regulator circuit of claim 17, wherein the multiplexer comprises: a plurality of native NMOS devices, each native NMOS device is coupled to a corresponding power source from the plurality of power sources. ### Claim 19 (depends on 18) The voltage regulator circuit of claim 18, wherein the multiplexer comprises: a first PMOS device coupled to the corresponding power source from the plurality of power sources; and a second PMOS device coupled to the first PMOS device and a corresponding native NMOS device from the plurality of native NMOS devices. ### Claim 20 (depends on 1) The voltage regulator circuit of claim 1, wherein at least one of the plurality of parallel low voltage regulators includes a low dropout regulator. ### Claim 21 A voltage regulator circuit, comprising: a multiplexer configured to select a respective power source from a plurality of power sources, wherein the multiplexer includes a plurality of native NMOS devices, each native NMOS device being coupled to a corresponding power source from the plurality of power sources; a high voltage linear regulator configured to receive the power source and to provide an intermediate voltage; and a plurality of parallel low voltage regulators coupled to the high voltage linear regulator configured to provide a regulated output voltage based upon the intermediate voltage. ### Claim 22 (depends on 21) The voltage regulator circuit of claim 21, wherein the multiplexer comprises: a first PMOS device coupled to the corresponding power source from the plurality of power sources; and a second PMOS device coupled to the first PMOS device and a corresponding native NMOS device from the plurality of native NMOS devices. ### Claim 23 (depends on 21) The voltage regulator circuit of claim 21, wherein each of the plurality of parallel low voltage regulators is configured to receive the intermediate voltage. ### Claim 24 (depends on 21) The voltage regulator circuit of claim 21, wherein the plurality of power sources is received from at least one of: a main battery, a recharger, and a backup battery. ### Claim 25 (depends on 21) The voltage regulator circuit of claim 21, wherein at least one of the plurality of parallel low voltage regulators is a low dropout voltage regulator. ### Claim 26 (depends on 21) The voltage regulator circuit of claim 21, wherein at least one of the plurality of parallel low voltage regulators has a dropout voltage of not more than approximately 14 millivolts for an output current from 0 to 50 mA. ### Claim 27 (depends on 21) The voltage regulator circuit of claim 21, wherein at least one of the plurality of parallel low voltage regulators comprises: a first stage configured to receive a reference voltage and to include a first current flowing through the first stage; a second stage, coupled to the first stage, configured to include a second current flowing through the second stage; and a third stage, coupled to the second stage, configured to output an output voltage and include a third current flowing through the third stage, wherein the first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and a maximum output current.