# US 7,745,942 B2 · Die package and probe card structures and fabrication methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,745,942 B2 - Document ID: US7745942B2 - Status: Granted - Kind: B2 - Application number: 11/472,010 - Filed: 2006-06-21 - Published: 2007-12-27 - Granted: 2010-06-29 - Earliest claimed: 2006-06-21 - Assignees: Micron Technology, Inc. - Inventors: David R. Hembree - Web page: https://patentgrep.com/patent/US7745942B2 ## CPC - G01R 1/07314: {the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support (on an elastic support, e.g. a film, G01R1/0735)} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 72/077: {Connecting of TAB connectors} - H10W 90/00: Package configurations - B33Y 80/00: Products made by additive manufacturing - G01R 3/00: Apparatus or processes specially adapted for the manufacture {or maintenance} of measuring instruments {, e.g. of probe tips} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/075: {of bond wires} - H10W 72/07532: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/251: {Materials} - H10W 72/50: Bond wires - H10W 72/534: {being rectangular} - H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/581: {Auxiliary members, e.g. flow barriers} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/701: {Tape-automated bond [TAB] connectors} - H10W 72/834: {Interconnections on sidewalls of chips} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/284: {characterised by structural arrangements for measuring or testing} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B33Y: ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING ## Abstract A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one or more peripheral edges where the conductor ends are disposed at a side surface of the dielectric material. Stacks of such semiconductor dice, wherein one of the dice is configured with discrete conductive elements projecting from the active surface, and the exposed ends of the dice in the stack are connected with vertical interconnects. A probe card is disclosed having bond wires extending from one or more central contacts between one or more peripheral contacts to the edge of the probe card. A probe card having an upper layer bearing contacts and at least one window therethrough, a lower layer bearing conductive traces with ends exposed through the at least one window, and conductors extending from at least some of the contacts to conductive trace ends is also provided. Methods of making the foregoing structures are disclosed. ## Claims ### Claim 1 A semiconductor device package, comprising: at least one semiconductor die assembly, comprising: a semiconductor die having an active surface with a plurality of bond pads disposed thereon; at least some bond pads of the plurality having conductors extending therefrom over the active surface to at least one peripheral edge of the semiconductor die; and dielectric material surrounding the conductors, extending to the at least one peripheral edge of the semiconductor die and having ends of the conductors exposed at the at least one peripheral edge of the semiconductor die assembly. ### Claim 2 (depends on 1) The semiconductor device package of claim 1, wherein the conductors comprise bond wires. ### Claim 3 (depends on 2) The semiconductor device package of claim 2, wherein the dielectric material comprises a dielectric layer encapsulating the bond wires. ### Claim 4 (depends on 3) The semiconductor device package of claim 3, wherein at least some of the bond wires include loop portions extending away from the active surface and having distal ends thereof exposed proximate a surface of the at least one dielectric layer above the active surface. ### Claim 5 (depends on 4) The semiconductor device package of claim 4, wherein the bond wires are configured to increase exposed wire area at the distal ends of the loop. ### Claim 6 (depends on 4) The semiconductor device package of claim 4, further comprising discrete conductive elements connected to the distal ends of the loop portions and protruding from the surface of the dielectric layer above the active surface. ### Claim 7 (depends on 3) The semiconductor device package of claim 3, further including at least one guide post comprising a dielectric material extending from the active surface and engaging a bond wire at a location intermediate the bond pad from which the bond wire extends and a peripheral edge of the semiconductor die. ### Claim 8 (depends on 3) The semiconductor device package of claim 3, further including at least one guide comb element comprising a dielectric material extending from the active surface at a location proximate a peripheral edge of the semiconductor die and engaging a bond wire. ### Claim 9 (depends on 3) The semiconductor device package of claim 3, further including at least one jumper pad at a location proximate a peripheral edge of the semiconductor die and having a bond wire affixed thereto. ### Claim 10 (depends on 3) The semiconductor device package of claim 3, further including at least one post comprising a dielectric material extending from the active surface, positioned at an intended outer lead bond (OLB) location over the active surface and engaging a portion of a bond wire. ### Claim 11 (depends on 10) The semiconductor device package of claim 10, further including at least one guide post comprising a dielectric material extending from the active surface and engaging a bond wire at a location intermediate the bond pad from which the bond wire extends and the at least one post positioned at the intended OLB location. ### Claim 12 (depends on 11) The semiconductor device package of claim 11, further including at least one guide comb element comprising a dielectric material extending from the active surface at a location proximate a peripheral edge of the semiconductor die and engaging a bond wire extending from the at least one post positioned at the intended OLB location. ### Claim 13 (depends on 11) The semiconductor device package of claim 11, further including at least one jumper pad at a location proximate a peripheral edge of the semiconductor die and having a bond wire extending from the at least one post positioned at the intended OLB location affixed thereto. ### Claim 14 (depends on 10) The semiconductor device package of claim 10, further comprising a discrete conductive element disposed on the at least one post positioned at the intended OLB location and in electrical contact with the portion of the bond wire engaged thereby. ### Claim 15 (depends on 1) The semiconductor device package of claim 1, wherein the conductors comprise electrically conductive traces. ### Claim 16 (depends on 15) The semiconductor device package of claim 15, wherein each conductive trace lies partially over a bond pad and extends toward the peripheral edge of the semiconductor die in either a trench formed in a layer of dielectric material disposed on the active surface or over an exposed surface of the layer of dielectric material, and further comprising another layer of dielectric material extending over the layer of dielectric material and the conductive traces. ### Claim 17 (depends on 15) The semiconductor device package of claim 15, wherein each conductive trace exhibits at least one of an increased depth and an increased width proximate a peripheral edge of the semiconductor die to which that conductive trace extends. ### Claim 18 (depends on 15) The semiconductor device package of claim 15, wherein each conductive trace has in contact therewith proximate a peripheral edge of the semiconductor die to which that trace extends, a portion of a conductive bump sectioned during singulation of the semiconductor die and providing increased conductive surface area for external electrical connection of that trace. ### Claim 19 (depends on 15) The semiconductor device package of claim 15, wherein at least some of the conductive traces each comprise an enlarged pad at an intended OLB location on the active surface intermediate the bond pad from which each of the at least some conductive traces extend and a peripheral edge of the semiconductor die, and further including a discrete conductive element in contact with each enlarged pad and projecting from a surface of the dielectric material above the active surface. ### Claim 20 (depends on 1) The semiconductor device package of claim 1, wherein each of the plurality of bond pads is disposed along a longitudinal axis of the at least one semiconductor die, and a conductor of the conductors extending from each bond pad extends toward a different peripheral edge than a conductor of the conductors extending toward a peripheral edge from at least one immediately adjacent bond pad. ### Claim 21 A semiconductor device package, comprising: a plurality of semiconductor die assemblies in a stack, each semiconductor die assembly of the plurality of semiconductor die assemblies comprising: a semiconductor die having an active surface with a plurality of bond pads disposed thereon; at least some bond pads of the plurality having conductors extending therefrom over the active surface to at least one peripheral edge of the semiconductor die; and dielectric material surrounding the conductors, extending to the at least one peripheral edge of the die and having ends of the conductors exposed at a side surface thereof; and interconnects comprising conductive paths extending between the exposed ends of the conductors of at least one semiconductor die assembly of the plurality of semiconductor die assemblies in the stack and at least another semiconductor die assembly of the plurality of semiconductor die assemblies in the stack. ### Claim 22 (depends on 21) The semiconductor device package of claim 21, wherein the at least one semiconductor die assembly of the plurality of semiconductor die assemblies further comprises a plurality of discrete conductive elements connected to at least some of the conductors thereof and projecting from a surface of the dielectric material above the active surface of the at least one semiconductor die assembly of the plurality of semiconductor die assemblies. ### Claim 23 (depends on 21) The semiconductor device package of claim 21, wherein the plurality of semiconductor die assemblies in the stack is oriented transversely to a plane of a carrier substrate having conductors, and wherein the exposed ends of the conductors at the side surface of the dielectric material of at least one of the plurality of semiconductor die assemblies are connected to at least some of the conductors of the carrier substrate. ### Claim 24 (depends on 23) The semiconductor device package of claim 23, wherein at least some of the exposed ends of the conductors at the side surface of the dielectric material of one semiconductor die assembly of the plurality of semiconductor die assemblies in the stack are aligned with at least some of the exposed ends of the conductors at the side surface of the dielectric material of at least another semiconductor die assembly of the plurality of semiconductor die assemblies in the stack, and further comprising interconnects comprising conductive paths extending between aligned exposed ends of the conductors of the at least one semiconductor die assembly of the plurality of semiconductor die assemblies and the at least another semiconductor die assembly of the plurality of semiconductor die assemblies. ### Claim 25 (depends on 23) The semiconductor device package of claim 23, wherein the carrier substrate is selected from the group consisting of a lead frame, a printed circuit board substrate, and an interposer substrate. ### Claim 26 (depends on 25) The semiconductor device package of claim 25, wherein the carrier substrate comprises a lead frame, and the conductors comprise leads. ### Claim 27 (depends on 25) The semiconductor device package of claim 25, wherein the carrier substrate comprises a printed circuit board substrate, and the conductors comprise conductive traces. ### Claim 28 (depends on 25) The semiconductor device package of claim 25, wherein the carrier substrate comprises an interposer substrate, the conductors comprise conductive traces, and the interposer substrate includes discrete conductive elements connected to the conductive traces for external connection of the package. ### Claim 29 (depends on 28) The semiconductor device package of claim 28, wherein the discrete conductive elements are selected from the group consisting of bumps, balls, studs, columns, pillars, pins and lands. ### Claim 30 (depends on 1) The semiconductor device package of claim 1, wherein: the conductors comprise bond wires, the bond wires having loop portions with distal ends thereof exposed proximate a surface of the dielectric material at intended OLB locations above the active surface; and the semiconductor device package further comprises discrete conductive elements disposed over and in contact with the distal ends and projecting from the surface of the dielectric material above the active surface. ### Claim 31 (depends on 30) The semiconductor device package of claim 30, wherein the dielectric material comprises a dielectric layer encapsulating the bond wires. ### Claim 32 (depends on 30) The semiconductor device package of claim 30, wherein the bond wires are configured to increase exposed wire area at the distal ends of the loop. ### Claim 33 (depends on 30) The semiconductor device package of claim 30, further including at least one guide post comprising a dielectric material extending from the active surface and engaging a bond wire at a location intermediate the bond pad from which the bond wire extends and a peripheral edge of the semiconductor die. ### Claim 34 (depends on 30) The semiconductor device package of claim 30, further including at least one guide comb element comprising a dielectric material extending from the active surface at a location proximate a peripheral edge of the semiconductor die and engaging a bond wire. ### Claim 35 (depends on 30) The semiconductor device package of claim 30, further including at least one jumper pad at a location proximate a peripheral edge of the semiconductor die and having a bond wire affixed thereto. ### Claim 36 (depends on 30) The semiconductor device package of claim 30, further including at least one post comprising a dielectric material extending from the active surface, positioned at an intended OLB location over the active surface and engaging a portion of a bond wire. ### Claim 37 (depends on 36) The semiconductor device package of claim 36, further including at least one guide post comprising a dielectric material extending from the active surface and engaging a bond wire at a location intermediate the bond pad from which the bond wire extends and the at least one post positioned at the intended OLB location. ### Claim 38 (depends on 36) The semiconductor device package of claim 36, further including at least one guide comb element comprising a dielectric material extending from the active surface at a location proximate a peripheral edge of the semiconductor die and engaging a bond wire extending from the at least one post positioned at the intended OLB location. ### Claim 39 (depends on 36) The semiconductor device package of claim 36, further including at least one jumper pad at a location proximate a peripheral edge of the semiconductor die and having a bond wire extending from the at least one post positioned at the intended OLB location affixed thereto. ### Claim 40 (depends on 30) The semiconductor device package of claim 30, wherein the intended OLB locations comprise a two-dimensional array over the active surface. ### Claim 41 (depends on 21) The semiconductor device package of claim 21, wherein the exposed ends of the conductors of at least one semiconductor die assembly of the plurality of semiconductor die assemblies in the stack are vertically aligned with the exposed ends of the conductors of at least another semiconductor die assembly of the plurality of semiconductor die assemblies in the stack.