# US 7,745,940 B2 · Forming ultra dense 3-D interconnect structures

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- Number: US 7,745,940 B2
- Document ID: US7745940B2
- Status: Granted
- Kind: B2
- Application number: 11/673,375
- Filed: 2007-02-09
- Published: 2007-06-28
- Granted: 2010-06-29
- Earliest claimed: 2005-12-28
- Assignees: Intel Corporation
- Inventors: Patrick R. Morrow
- Web page: https://patentgrep.com/patent/US7745940B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at least one of an active feature and an interconnect structure disposed within the first substrate, and forming a reactive material on a surface of at least one of the active features.

## Claims

### Claim 1

A structure comprising:
at least one bond pad of a device side of a first substrate coupled to at least one bond pad of a device side of a second substrate, wherein the second substrate comprises at least one of a gate and a source/drain;
a via extending through the non-device side of the first substrate and disposed directly on a second side of a gate and a source/drain disposed within the first substrate, wherein the via comprises a dielectric lining on an inner portion of the via; and
a silicide confined within the via on the second side of the one of the gate and the source/drain.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the via comprises a conductive material.

### Claim 3 (depends on 2)

The structure of claim 2 wherein the conductive material comprises at least one of tungsten and copper.

### Claim 4 (depends on 2)

The structure of claim 2 wherein the conductive material further comprises at least one bonding pad on a top surface of the conductive material.

### Claim 5 (depends on 1)

The structure of claim 1 wherein a dielectric layer is disposed on a top surface of the non-device side of the first substrate.

### Claim 6 (depends on 1)

The structure of claim 1 wherein at least one of the first substrate and the second substrate comprise a silicon on insulator substrate.

### Claim 7 (depends on 1)

The structure of claim 1 wherein at least one of the first substrate and the second substrate comprise a silicon on insulator substrate.

### Claim 8 (depends on 1)

The structure of claim 1 further comprising a system comprising:
a bus communicatively coupled to the structure; and
a DRAM communicatively coupled to the bus.