# US 7,745,935 B2 · Method to create super secondary grain growth in narrow trenches

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,745,935 B2
- Document ID: US7745935B2
- Status: Granted
- Kind: B2
- Application number: 12/252,764
- Filed: 2008-10-16
- Published: 2009-04-23
- Granted: 2010-06-29
- Earliest claimed: 2006-04-10
- Assignees: Imec
- Inventors: Gerald Beyer; Sywert H. Brongersma
- Web page: https://patentgrep.com/patent/US7745935B2

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10P 14/412: {Deposition of metallic or metal-silicide materials}
- H10P 14/44: Physical vapour deposition [PVD]
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W 20/033: {in openings in dielectrics}
- H10W 20/055: {by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition}
- H10W 20/0552: {by diffusing metallic dopants to react with dielectrics}
- H10W 20/064: {by modifying the conductivity of conductive parts, e.g. by alloying}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4421: {the principal metal being copper}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.

## Claims

### Claim 1

A semiconductor device comprising at least one structure selected from the group consisting of a trench and a via, wherein the structure is filled with recrystallized electrochemically deposited copper, wherein at least 80% of said recrystallized electrochemically deposited copper consists of copper grains having a [100] orientation and dimensions of at least 10 microns.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein at least 93% of said recrystallized electrochemically deposited copper consists of said copper grains having a [100] orientation and dimensions of at least 10 microns.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein at least 98% of said recrystallized electrochemically deposited copper consist of said copper grains having a [100] orientation and dimensions of at least 10 micron.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein said copper grains with a [100] orientation have dimensions of at least 25 micrometers.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein said copper grains with a [100] orientation have dimensions of at least 100 micrometers.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein said structure is a trench, and wherein said trench has a width of from 50 nm to 200 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein said structure is a trench, and wherein said trench has a width of less than 200 nm.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein said trench has an aspect ratio or a height to width ratio higher than 1.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein said recrystallized electrochemically deposited copper is laid upon a diffusion barrier layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein said diffusion barrier layer has a thickness of less than 8 nm.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein said diffusion barrier layer is a layer comprising a metal selected from the group consisting of tantalum, titanium, ruthenium, tungsten, manganese, and combinations thereof.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein said diffusion barrier layer comprises a material selected from the group consisting of α-tantalum, β-tantalum, tantalum nitride, and combinations thereof.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising a copper seedlayer atop said diffusion barrier layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein said copper seedlayer is a manganese-containing seedlayer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein said diffusion barrier layer comprises manganese.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, having a surface that has been subjected to chemical mechanical polishing.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the structure is a via.