# US 7,745,931 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 7,745,931 B2
- Document ID: US7745931B2
- Status: Granted
- Kind: B2
- Application number: 10/855,974
- Filed: 2004-05-28
- Published: 2005-01-06
- Granted: 2010-06-29
- Earliest claimed: 2003-06-09
- Assignees: Sanyo Electric Co., Ltd.
- Inventors: Yukihiro Takao
- Web page: https://patentgrep.com/patent/US7745931B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/251: {Materials}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A BGA type semiconductor device having high reliability is offered. A pad electrode is formed on a surface of a semiconductor substrate and a glass substrate is bonded to the surface of the semiconductor substrate. A via hole is formed from a back surface of the semiconductor substrate to reach a surface of the pad electrode. An insulation film is formed on an entire back surface of the semiconductor substrate including an inside of the via hole. A cushioning pad is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole by etching. A wiring connected with the pad electrode is formed to extend from the via hole onto the cushioning pad. A conductive terminal is formed on the wiring. Then the semiconductor substrate is separated into a plurality of semiconductor dice.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having a via hole;
a pad electrode disposed on a first surface of the semiconductor substrate, the pad electrode covering the via hole and extending to a dicing line region of the semiconductor device, the via hole connecting a second surface of the semiconductor substrate and a surface of the pad electrode covering the via hole;
a passivation film formed on the pad electrode;
a supporting substrate bonded to the first surface of the semiconductor substrate;
a wiring contacting the surface of the pad electrode covering the via hole through the via hole and extending over the second surface of the semiconductor substrate from the via hole; and
a conductive terminal formed on the wiring extending over the second surface of the semiconductor substrate,
wherein the pad electrode is disposed between the passivation film and the first surface of the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising an insulation film formed on a sidewall of the via hole to electrically isolate the wiring from the semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the following conditions are met:
0.7Ks≦Kg≦1.3Ks
where Kg denotes a thermal expansion coefficient of the supporting substrate and Ks denotes a thermal expansion coefficient of the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the supporting substrate is a glass substrate on which no wiring is formed.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a resin layer bonding the supporting substrate to the passivation film formed on the pad electrode.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the wiring completely fills the via hole.

### Claim 7

A semiconductor device comprising:
a semiconductor substrate having a via hole;
a pad electrode disposed on a first surface of the semiconductor substrate, the pad electrode covering the via hole and extending to a dicing line region of the semiconductor device the via hole connecting a second surface of the semiconductor substrate and a surface of the pad electrode covering the via hole;
a passivation film formed on the pad electrode; and
a wiring contacting the surface of the pad electrode covering the via hole through the via hole and extending over the second surface of the semiconductor substrate from the via hole,
wherein the pad electrode is disposed between the passivation film and the first surface of the semiconductor substrate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising an insulation film formed on a sidewall of the via hole to electrically isolate the wiring from the semiconductor substrate.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the wiring completely fills the via hole.