# US 7,745,930 B2 · Semiconductor device packages with substrates for redistributing semiconductor device electrodes

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- Number: US 7,745,930 B2
- Document ID: US7745930B2
- Status: Granted
- Kind: B2
- Application number: 11/409,679
- Filed: 2006-04-24
- Published: 2006-11-23
- Granted: 2010-06-29
- Earliest claimed: 2005-04-25
- Assignees: International Rectifier Corporation
- Inventors: Norman Glyn Connah; Mark Pavier; Phillip Adamson; Hazel D Schofield
- Web page: https://patentgrep.com/patent/US7745930B2

## CPC

- H10W 70/467: {Multilayered additional interconnections}
- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H10W 40/10: Arrangements for heating
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 40/778: {in encapsulations}
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/468: {Circuit boards}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 70/692: Ceramics or glasses
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40)
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 72/075: {of bond wires}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/07553: {changes in shapes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/537: {Multiple bond wires having different shapes}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/881: {Bump connectors and strap connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.

## Claims

### Claim 1

A semiconductor device package comprising:
a power semiconductor device having a first major surface, a second major surface, a first edge extending along a first direction, and a second edge extending along a second direction, said first edge being opposite said second edge;
a first elongated runner over said first major surface of said power semiconductor device and extending along said first direction;
a second elongated runner over said first major surface of said power semiconductor device and extending along said second direction;
a plurality of first power electrodes and a plurality of second power electrodes on said first major surface of said power semiconductor device, said first power electrodes being electrically connected to said first elongated runner and said second power electrodes being electrically connected to said second elongated runner, said first power electrodes and said second power electrodes being disposed between said first elongated runner and said second elongated runner;
a substrate having a first major surface and a second major surface, said second major surface of said power semiconductor device being thermally coupled to said first major surface of said substrate;
a first conductive pad and a second conductive pad disposed on said first major surface of said substrate, said first conductive pad extending along said first edge of said power semiconductor device and said second conductive pad extending along said second edge of said power semiconductor device;
a plurality of spaced first wirebonds connected to said first elongated runner and said first conductive pad;
a plurality of spaced second wirebonds connected to said second elongated runner and said second conductive pad;
a first external lead electrically and mechanically coupled to said first conductive pad by a conductive adhesive;
a second external lead electrically and mechanically coupled to said second conductive pad by a conductive adhesive; and
a molded housing enclosing at least said power semiconductor device and at least a portion of said first major surface of said substrate.

### Claim 2 (depends on 1)

The semiconductor device package according to claim 1, wherein said substrate and said first and second conductive pads constitute an insulated metal substrate.

### Claim 3 (depends on 1)

The semiconductor device package according to claim 1, wherein said substrate is comprised of a ceramic.

### Claim 4 (depends on 1)

The semiconductor device package according to claim 1, further comprising a heat spreader thermally connected to said second major surface of said power semiconductor device.

### Claim 5 (depends on 1)

The semiconductor device package according to claim 1, wherein said package conforms to a TO package format.

### Claim 6 (depends on 1)

The semiconductor device package according to claim 1, wherein said package conforms to a single inline package format.

### Claim 7 (depends on 1)

The semiconductor device package according to claim 1, wherein said package conforms to a SO package format.

### Claim 8 (depends on 1)

The semiconductor device package according to claim 1, further comprising at least a third external lead, wherein each external lead extends beyond an outer boundary of said housing along a single common edge and is adjacent to one or more other external leads, and wherein a spatial separation between one pair of adjacent leads is greater than a spatial separation between each other pair of adjacent leads.

### Claim 9 (depends on 1)

The semiconductor device package according to claim 1, further comprising:
a third conductive pad disposed on said first major surface of said substrate;
a control electrode on said first major surface of said semiconductor device, said control electrode being electrically connected to said third conductive pad; and
an external lead electrically connected to said third conductive pad;
wherein said external lead electrically connected to said first conductive pad and
said external lead electrically connected to said second conductive pad are wide leads and have a width larger than said external lead connected to said third conductive pad.

### Claim 10 (depends on 1)

The semiconductor device package according to claim 1, wherein said plurality of first wirebonds and said plurality of second wirebonds are parallel to one another and of same length.

### Claim 11 (depends on 1)

The semiconductor device package according to claim 1, further comprising a heat spreader in thermal contact with said second major surface of said substrate.

### Claim 12 (depends on 1)

The semiconductor device package according to claim 1, further comprising:
a third conductive pad disposed on said first major surface of said substrate; and
a control electrode on said first major surface of said power semiconductor device,
said control electrode being electrically connected to said third conductive pad.

### Claim 13 (depends on 12)

The semiconductor device package according to claim 12, further comprising:
a fourth conductive pad disposed on said first major surface of said substrate; and
a second control electrode on said first major surface of said power semiconductor device, said second control electrode being electrically connected to said fourth conductive pad.

### Claim 14 (depends on 1)

The semiconductor device package according to claim 1, wherein said first power electrode and said second power electrode are interdigitated.

### Claim 15 (depends on 1)

The semiconductor device package according to claim 1, wherein said second major surface of said power semiconductor device is electrically nonconductive.

### Claim 16 (depends on 1)

The semiconductor device package according to claim 1, wherein said power semiconductor device is a III-nitride based device.

### Claim 17 (depends on 16)

The semiconductor device package according to claim 16, wherein said power semiconductor device is a GaN based device.