# US 7,745,922 B2 · Package board having internal terminal interconnection and semiconductor package employing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,745,922 B2 - Document ID: US7745922B2 - Status: Granted - Kind: B2 - Application number: 11/424,605 - Filed: 2006-06-16 - Published: 2007-07-19 - Granted: 2010-06-29 - Earliest claimed: 2006-01-19 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Jong-Joo Lee - Web page: https://patentgrep.com/patent/US7745922B2 ## CPC - H10W 72/00: Interconnections or connectors in packages - H10W 70/685: comprising multiple insulating layers - H10W 76/13: Containers comprising a conductive base serving as an interconnection - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided. ## Claims ### Claim 1 A package board comprising: a board body having a front surface and a back surface; a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body; a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and an internal terminal interconnection disposed in a bulk region of the board body or on a surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad, wherein the first internal terminal pad and the second internal terminal pad are electrically insulated from the first power pad, the first ground pad and the first signal pad. ### Claim 2 (depends on 1) The package board according to claim 1, further comprising a common power interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second power pads. ### Claim 3 (depends on 2) The package board according to claim 2, wherein the internal terminal interconnection is disposed across the common power interconnection and electrically insulated from the common power interconnection. ### Claim 4 (depends on 1) The package board according to claim 1, further comprising a common ground interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second ground pads. ### Claim 5 (depends on 4) The package board according to claim 4, wherein the internal terminal interconnection is disposed across the common ground interconnection and electrically insulated from the common ground interconnection. ### Claim 6 (depends on 1) The package board according to claim 1, wherein the first power pad, the first ground pad and the first signal pad are electrically connected to the second power pad, the second ground pad and the second signal pad, respectively, through first, second and third holes penetrating the board body. ### Claim 7 (depends on 1) The package board according to claim 1, wherein the first internal terminal pad and the second internal terminal pad are directly connected to a first internal bonding pad and a second internal bonding pad of a semiconductor chip to be mounted on the front surface of the board body. ### Claim 8 (depends on 2) The package board according to claim 2, wherein the internal terminal interconnection and the common power interconnection are electrically insulated from each other. ### Claim 9 (depends on 1) The package board according to claim 1, wherein the first internal terminal pad and the second internal terminal pad are only disposed on the front surface of the board body. ### Claim 10 A semiconductor package comprising: a board body having a front surface and a back surface; a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body; a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; a power ball, a ground ball and a signal ball that are in contact with the second power pad, the second ground pad and the second signal pad, respectively; an internal terminal interconnection disposed in a bulk region of the board body or on a surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad; a semiconductor chip mounted on the front surface of the board body, the semiconductor chip having an external power bonding pad, an external ground bonding pad, an external signal bonding pad, a first internal bonding pad and a second internal bonding pad; and an external power connector, an external ground connector, an external signal connector, a first internal connector and a second internal connector electrically connecting the first power pad, the first ground pad, the first signal pad, the first internal terminal pad and the second internal terminal pad to the external power bonding pad, the external ground bonding pad, the external signal bonding pad, the first internal bonding pad and the second internal bonding pad, respectively, wherein the first internal terminal pad and the second internal terminal pad are electrically insulated from the first power pad, the first ground pad and the first signal pad. ### Claim 11 (depends on 10) The package according to claim 10, further comprising a common power interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second power pads. ### Claim 12 (depends on 10) The package according to claim 10, further comprising a common ground interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second ground pads. ### Claim 13 (depends on 10) The package according to claim 10, wherein the first power pad, the first ground pad and the first signal pad are electrically connected to the second power pad, the second ground pad and the second signal pad, respectively, through first, second and third holes penetrating the board body. ### Claim 14 (depends on 10) The package according to claim 10, wherein the first internal bonding pad is electrically connected to an output terminal of an internal power generator of the semiconductor chip, and wherein the second internal bonding pad is electrically connected to a power terminal of any one of one or more internal circuits of the semiconductor chip. ### Claim 15 (depends on 10) The package according to claim 10, wherein the semiconductor chip is a flip chip. ### Claim 16 (depends on 15) The package according to claim 15, wherein the external power connector, the external ground connector, the external signal connector, the first internal connector and the second internal connector are flip chip bumps. ### Claim 17 (depends on 11) The semiconductor package according to claim 11, wherein the first internal connector and the second internal connector are electrically insulated from the common power interconnection. ### Claim 18 A semiconductor package comprising: a board body having a front surface and a back surface; a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body; a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; a power ball, a ground ball and a signal ball that are in contact with the second power pad, the second ground pad and the second signal pad, respectively; an internal terminal interconnection disposed in a bulk region of the board body or on a surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad; a semiconductor chip mounted on the front surface of the board body, the semiconductor chip having an external power bonding pad, an external ground bonding pad, an external signal bonding pad, a first internal bonding pad and a second internal bonding pad; and an external power connector, an external ground connector, an external signal connector, a first internal connector and a second internal connector electrically connecting the first power pad, the first ground pad, the first signal pad, the first internal terminal pad and the second internal terminal pad to the external power bonding pad, the external ground bonding pad, the external signal bonding pad, the first internal bonding pad and the second internal bonding pad, respectively, wherein the semiconductor chip comprises: a semiconductor substrate; internal circuits formed at the semiconductor substrate; an insulating layer covering the internal circuits and the semiconductor substrate; an external power chip pad, an external ground chip pad, an external signal chip pad, a first internal chip pad and a second internal chip pad disposed on the insulating layer and electrically connected to the internal circuits; a dielectric layer covering the insulating layer and the chip pads; and a power line, a ground line, a signal line, a first interconnection and a second interconnection redistributed on the dielectric layer and electrically connected to the external power chip pad, the external ground chip pad, the external signal chip pad, the first internal chip pad and the second internal chip pad, respectively, wherein a portion of the redistributed power line, a portion of the redistributed ground line, a portion of the redistributed signal line, a portion of the first interconnection and a portion of the second interconnection correspond to the external power bonding pad, the external ground bonding pad, the external signal bonding pad, the first internal bonding pad and the second internal bonding pad, respectively. ### Claim 19 (depends on 18) The package according to claim 18, further comprising an internal interconnection disposed on or in the insulating layer, wherein the internal interconnection electrically connects the first internal chip pad to the second internal chip pad. ### Claim 20 (depends on 18) The package according to claim 18, wherein the one or more internal circuits are configured as a DRAM circuit. ### Claim 21 (depends on 20) The package according to claim 20, wherein the DRAM circuit comprises a well bias circuit, a high voltage generator and a plate electrode voltage generator. ### Claim 22 (depends on 21) The package according to claim 21, wherein one of the first internal chip pad and the second internal chip pad is electrically connected to an output terminal of any one of the well bias circuit, the high voltage generator and the plate electrode voltage generator. ### Claim 23 (depends on 18) The package according to claim 18, further comprising a redistributed internal interconnection provided on the dielectric layer to electrically connect the first internal bonding pad to the second internal bonding pad.