# US 7,745,917 B2 · Compliant integrated circuit package substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,745,917 B2 - Document ID: US7745917B2 - Status: Granted - Kind: B2 - Application number: 12/701,142 - Filed: 2010-02-05 - Published: 2010-06-03 - Granted: 2010-06-29 - Earliest claimed: 2006-06-27 - Assignees: Intel Corporation - Inventors: Biju Chandran; Mitul Modi - Web page: https://patentgrep.com/patent/US7745917B2 ## CPC - H10W 70/68: Shapes or dispositions thereof - H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components} - H10W 74/117: {the substrate having spherical bumps for external connection} - H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion} - H05K 2201/09036: Recesses or grooves in insulating substrate - H05K 2201/10734: Ball grid array [BGA]; Bump grid array - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression. ## Claims ### Claim 1 An integrated circuit package comprising: a plurality of interconnects; and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core, wherein a first surface of the integrated circuit package substrate core defines a depression entirely filled with a dielectric, wherein a second surface of the integrated circuit package substrate core defines a second depression entirely filled with the dielectric, and wherein the second depression substantially mirrors the depression through the integrated circuit package substrate core. ### Claim 2 (depends on 1) An integrated circuit package according to claim 1, wherein the depression comprises an open end and a closed end, wherein the second depression comprises a second open end and a second closed end, and wherein the closed end is closer to the second closed end than to the second open end. ### Claim 3 (depends on 1) An integrated circuit package according to claim 1, wherein the depression is disposed adjacent to a corner of the integrated circuit package substrate core, and wherein the depression facilitates flexing of the corner. ### Claim 4 (depends on 1) An integrated circuit package according to claim 1, wherein the depression comprises a continuous loop substantially following a periphery of the integrated circuit package substrate core. ### Claim 5 (depends on 1) An integrated circuit package according to claim 1, wherein the integrated circuit package substrate core comprises an outer core layer and an inner core layer, and wherein the depression extends through the outer core layer and into the inner core layer. ### Claim 6 (depends on 5) An integrated circuit package according to claim 5, wherein the outer core layer comprises a metal, and wherein the inner core layer comprises a fiber-reinforced material. ### Claim 7 (depends on 1) An integrated circuit package according to claim 1, wherein the integrated circuit package substrate core comprises an outer core layer and an inner core layer, and wherein the depression extends through the outer core layer and not into the inner core layer. ### Claim 8 (depends on 1) An integrated circuit package according to claim 1, the integrated circuit package substrate comprising a power plane including a non-conductive area, wherein the non-conductive area is disposed in relation to the depression to facilitate flexing of the integrated circuit package substrate. ### Claim 9 A system comprising: a microprocessor die; an integrated package substrate coupled to the microprocessor die and comprising an integrated circuit package substrate core; a plurality of interconnects coupled to the integrated package substrate; and a double data rate memory in communication with the microprocessor die, wherein a first surface of the integrated circuit package substrate core defines a depression entirely filled with a dielectric, wherein a second surface of the integrated circuit package substrate core defines a second depression entirely filled with the dielectric, and wherein the second depression substantially mirrors the depression through the integrated circuit package substrate core. ### Claim 10 (depends on 9) A system according to claim 9, wherein the depression comprises an open end and a closed end, wherein the second depression comprises a second open end and a second closed end, and wherein the closed end is closer to the second closed end than to the second open end. ### Claim 11 (depends on 9) A system according to claim 9, wherein the integrated circuit package substrate core comprises an outer core layer and an inner core layer, and wherein the depression extends through the outer core layer and into the inner core layer. ### Claim 12 (depends on 9) A system according to claim 9, wherein the integrated circuit package substrate core comprises an outer core layer and an inner core layer, and wherein the depression extends through the outer core layer and not into the inner core layer. ### Claim 13 (depends on 9) A system according to claim 9, the integrated circuit package substrate comprising a power plane including a non-conductive area, wherein the non-conductive area is disposed in relation to the depression to facilitate flexing of the integrated circuit package substrate.