# US 7,745,911 B2 · Semiconductor chip package

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- Number: US 7,745,911 B2
- Document ID: US7745911B2
- Status: Granted
- Kind: B2
- Application number: 12/155,867
- Filed: 2008-06-11
- Published: 2008-12-11
- Granted: 2010-06-29
- Earliest claimed: 2007-06-11
- Assignees: Samsung Electro-Mechanics Co., Ltd.
- Inventors: Tae Soo Lee; Yun Hwi Park
- Web page: https://patentgrep.com/patent/US7745911B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/682: {comprising holes having chips therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/692: Ceramics or glasses
- H10W 72/07236: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

## Claims

### Claim 1

A semiconductor chip package comprising:
a main board;
a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and
a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate,
wherein the ceramic substrate comprises:
at least one first ground line electrically connecting the conductive shielding layer with the main board;
at least one second ground line electrically connecting the conductive shielding layer with the chip; and
at least one signal line electrically connecting the chip with the main board.

### Claim 2 (depends on 1)

The semiconductor chip package of claim 1, wherein the conductive shielding layer covers a top surface and outer side surfaces of the ceramic substrate.

### Claim 3 (depends on 1)

The semiconductor chip package of claim 1, wherein the conductive shielding layer comprises bar-shaped patterns alternately disposed on a top surface of the ceramic substrate.

### Claim 4 (depends on 1)

The semiconductor chip package of claim 1, wherein the conductive shielding layer comprises a helical pattern on a top surface of the ceramic substrate.

### Claim 5 (depends on 1)

The semiconductor chip package of claim 1, wherein the first ground line comprises a first conductive via penetrating the ceramic substrate and electrically connecting the conductive shielding layer with a ground terminal of the main board.

### Claim 6 (depends on 1)

The semiconductor chip package of claim 1, wherein the second ground line comprises a second conductive via penetrating the ceramic substrate and electrically connecting the conductive shielding layer with a ground terminal of the chip.

### Claim 7 (depends on 1)

The semiconductor chip package of claim 1, wherein the signal line comprises:
an inner pattern provided in the ceramic substrate and electrically connected with a signal terminal of the chip; and
a signal via formed in the ceramic substrate and electrically connecting the inner pattern with a signal terminal of the main board.

### Claim 8 (depends on 1)

The semiconductor chip package of claim 1, wherein the cavity is filled with a resin filler covering and protecting the chip.

### Claim 9 (depends on 1)

The semiconductor chip package of claim 1, wherein the chip is mounted to the ceramic substrate by flip-chip bonding.