# US 7,745,906 B2 · Semiconductor device having spaced unit regions and heavily doped semiconductor layer

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- Number: US 7,745,906 B2
- Document ID: US7745906B2
- Status: Granted
- Kind: B2
- Application number: 11/550,189
- Filed: 2006-10-17
- Published: 2008-01-10
- Granted: 2010-06-29
- Earliest claimed: 2006-07-07
- Assignees: Mitsubishi Electric Corporation
- Inventors: Kazunari Hatade
- Web page: https://patentgrep.com/patent/US7745906B2

## CPC

- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a semiconductor region on a surface of said semiconductor substrate;
a first semiconductor layer region at a surface of said semiconductor region and coupled to a first electrode;
a second semiconductor layer region being of a ring-shaped form and located in said semiconductor region, the second semiconductor layer region being spaced from said first semiconductor layer region and surrounding said first semiconductor layer region, the second semiconductor layer region being different in conductivity type from said semiconductor region;
a third semiconductor layer region having a plurality of unit regions located in said second semiconductor layer region, the plurality of unit regions being spaced from each other at a predetermined interval and being different in conductivity type from said second semiconductor layer region, each of the unit regions having a rectangle-like form with a width larger than the predetermined interval, the third semiconductor layer region being different in conductivity type from said second semiconductor layer region;
a heavily doped semiconductor layer located in said second semiconductor layer region, at least below said third semiconductor layer region, the heavily doped semiconductor layer being doped more heavily than said second semiconductor layer region and being the same in conductivity type as said second semiconductor layer region;
a gate electrode layer above said semiconductor region and a part of said second semiconductor layer region and configured to form a channel, at a surface of the part of said second semiconductor layer region, extending so as to reach said semiconductor region from the third semiconductor layer region, for transferring charges between the semiconductor region and the third semiconductor layer region through said channel; and
a base layer located in said second semiconductor layer region, the base layer having been doped less heavily than said heavily doped semiconductor layer and being the same conductivity type as said heavily doped semiconductor layer, the heavily doped semiconductor layer extending farther toward the surface of said semiconductor substrate than does said base layer extend toward the surface of said semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an insulating layer between said semiconductor region and said semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein said semiconductor region consists of a single conductivity type.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an electrode adjoining the third semiconductor layer region, the heavily doped semiconductor layer, and the base layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the base layer includes an opposing region opposing the part of said second semiconductor layer region across said heavily doped semiconductor layer.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, further comprising:
an electrode adjoining the third semiconductor layer region, the heavily doped semiconductor layer, and the opposing region.