# US 7,745,904 B2 · Shallow trench isolation structure for semiconductor device

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- Number: US 7,745,904 B2
- Document ID: US7745904B2
- Status: Granted
- Kind: B2
- Application number: 11/809,519
- Filed: 2007-05-31
- Published: 2007-10-11
- Granted: 2010-06-29
- Earliest claimed: 2005-03-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Hsin Ko; Chung-Hu Ke; Chien-Chao Huang
- Web page: https://patentgrep.com/patent/US7745904B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.

## Claims

### Claim 1

A semiconductor device comprising a transistor formed on a semiconductor substrate and between a duality of opposed isolation trenches formed in the semiconductor substrate, each isolation trench filled with a dielectric, the transistor including a channel region formed within a section of the substrate surface, a gate structure overlying the channel region, and a source region and a drain region formed within the substrate adjacent opposed ends of the channel region and in a corresponding substrate portion that overhangs the corresponding isolation trench such that the drain region overhangs only one isolation trench and the source region overhangs only the other isolation trench, the substrate portion having a completely and continuously curved upper surface, wherein the completely and continuously curved upper surface of the substrate portion is entirely disposed at a height below a top planar surface of the dielectric.

### Claim 2 (depends on 1)

The semiconductor device as in claim 1, wherein the substrate portion overhangs the isolation trench by 10-2000 angstroms.

### Claim 3 (depends on 1)

The semiconductor device as in claim 1, wherein the completely and continuously curved upper surface of the substrate portion is entirely disposed at a height below a top planar surface of the semiconductor substrate.

### Claim 4 (depends on 3)

The semiconductor device as in claim 3, wherein the substrate portion includes a radius of curvature of 5-50 nanometers.

### Claim 5 (depends on 1)

The semiconductor device as in claim 1, wherein the source region and the drain region each comprise a silicide formed thereon.

### Claim 6 (depends on 1)

The semiconductor device as in claim 1, wherein the a gate structure comprises a gate dielectric material overlying the channel region and a gate electrode overlying the gate dielectric.

### Claim 7 (depends on 6)

The semiconductor device as in claim 6, wherein a silicide layer is formed on a surface of the transistor portion.

### Claim 8 (depends on 1)

The semiconductor device as in claim 1, wherein the isolation trench extends down from the substrate surface.