# US 7,745,890 B2 · Hybrid metal fully silicided (FUSI) gate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,745,890 B2
- Document ID: US7745890B2
- Status: Granted
- Kind: B2
- Application number: 11/863,804
- Filed: 2007-09-28
- Published: 2009-04-02
- Granted: 2010-06-29
- Earliest claimed: 2007-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Cheng-Tung Lin; Cheng-Hung Chang; Hsiang-Yi Wang; Chen-Nan Yeh
- Web page: https://patentgrep.com/patent/US7745890B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0174: {the gate conductors being silicided}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having a PMOS area and an NMOS area;
a dielectric layer on the PMOS area and NMOS area;
a mid-gap metal layer on the dielectric layer;
a PMOS gate electrode, wherein the PMOS gate electrode includes a first polysilicon region disposed on a P-metal layer which is disposed on the mid-gap metal layer; and
an NMOS gate electrode, wherein the NMOS gate electrode includes a second polysilicon region disposed on the mid-gap metal layer, and the second polysilicon region being fully silicided.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer material is selected from a group of HfO2, HfSiOx, SiO2, SiN, and combinations thereof.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the dielectric layer is a thickness of about 20 Å.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the mid-gap metal layer is selected from a group of TiN, TixWy, or TaN.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the mid-gap layer is a thickness of about 15 Å.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the P-metal is selected from a group of WNx, MoNx, TaAlyNx, TiAlyNx, TaCNO, and TiC.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the P-metal has a thickness of about 50 Å.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the polysilicon a thickness of about 600 Å.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the polysilicon surface is planerized using a chemical mechanical polish process.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the fully silicided second polysilicon region comprises Ni.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the Ni is a thickness of essentially 350 Å.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the fully silicided second polysilicon is a single phase NiSi.

### Claim 13

A system comprising:
a PMOS gate structure, the PMOS gate structure comprising:
a first high-κ dielectric layer;
a P-metal layer;
a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer and the P-metal layer; and
a fully silicided polysilicon layer formed on the P-metal layer; and
an NMOS gate structure, the NMOS gate structure comprising:
a second high-κ dielectric layer;
the fully silicided polysilicon layer; and
the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided polysilicon layer.

### Claim 14 (depends on 13)

The system of claim 13, wherein the first high-κ dielectric layer and the second high-κ dielectric layer are formed simultaneously.

### Claim 15 (depends on 13)

The system of claim 13, wherein the NMOS gate structure further comprises:
an N-metal layer, wherein the N-metal layer is disposed between the mid-gap metal layer and the fully silicided layer.

### Claim 16 (depends on 13)

The system of claim 13, wherein the high-κ dielectric layer comprises HfO2 about 20 Å thick.

### Claim 17 (depends on 13)

The system of claim 13, wherein the mid-gap metal layer comprises TiN about 15 Å thick.

### Claim 18 (depends on 13)

The system of claim 13, wherein the P-metal layer comprises TaCNO about 50 Å thick.

### Claim 19 (depends on 13)

The system of claim 13, wherein the fully silicided layer comprises single phase NiSi.

### Claim 20

A semiconductor device comprising:
a high-κ layer of HfO2 on a substrate, wherein the substrate includes a PMOS region and an NMOS region;
a TiN layer on the high-κ layer;
a TaCNO layer on the TiN layer in the PMOS region of the substrate;
a single phase fully silicided polysilicon gate stack region disposed on the TaCNO layer;
a single phase fully silicided polysilicon gate stack on the TiN layer; and
source/drain regions for both NMOS and PMOS transistors.