# US 7,745,887 B2 · Dual work function metal gate structure and related method of manufacture

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- Number: US 7,745,887 B2
- Document ID: US7745887B2
- Status: Granted
- Kind: B2
- Application number: 11/862,404
- Filed: 2007-09-27
- Published: 2008-01-24
- Granted: 2010-06-29
- Earliest claimed: 2005-02-22
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Min-Joo Kim; Hyung-Suk Jung; Jong-Ho Lee; Sungkee Han
- Web page: https://patentgrep.com/patent/US7745887B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine.

## Claims

### Claim 1

A semiconductor device, comprising at least one of:
a NMOS metal gate structure comprising a first metal gate electrode formed from a metal layer doped with fluorine to have a first work function; and,
a PMOS metal gate structure comprising a second metal gate electrode formed from the metal layer doped with carbon to have a second work function.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second work function is greater than the first work function.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the metal layer is doped with a Gaussian concentration profile of carbon atoms along the thickness of the metal layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the metal layer is doped with a Gaussian concentration profile of fluorine atoms along the thickness of the metal layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the at least one NMOS and PMOS metal gate structures comprises an additional conductive layer formed on the metal layer to define a profile height for the at least one NMOS and PMOS metal gate structures.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the metal layer is formed to a thickness of less than 100 Å.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the additional conductive layer is formed to a thickness of greater than 1000 Å.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first work function ranges from between about 3.7 to 4.5 eV, and wherein the second work function ranges from between about 4.7 to 5.3 eV.

### Claim 9

The semiconductor device, comprising:
NMOS and PMOS active regions formed in a substrate;
a gate insulating layer formed on the substrate over the NMOS and PMOS active regions;
a NMOS metal gate structure formed on the gate insulating layer over the NMOS active region and comprising a first metal gate electrode formed from a metal layer and doped with fluorine to have a first work function; and,
a PMOS metal gate structure formed on the gate insulating layer over the PMOS active region and comprising a second metal gate electrode formed from the metal layer and having a second work function greater than the first work function.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first work function ranges from between about 3.7 to 4.5 eV, and wherein the second work function ranges from between about 4.7 to 5.3 eV.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the metal layer comprises at least one of nickel (Ni), ruthenium oxide (RuO), molybdenum nitride (MoN), tantalum nitride (TaN), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), and tantalum nitride (TaN).

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the metal layer is formed using a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the NMOS and PMOS metal gate structures further comprise an additional conductive layer formed on the metal layer to define a profile height.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the metal layer is formed to a thickness of less than 100 Å, and the additional conductive layer is formed to a thickness of greater than 1000 Å.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the NMOS and PMOS metal gate structures comprise a stacked structure formed from a patterned portion of the additional conductive layer formed on a patterned portion of the metal layer formed on a patterned portion of the gate insulating layer, and gate spacers formed on sidewalls of the stacked structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising:
source and drain regions formed in the substrate on opposite sides of the NMOS and PMOS metal gate structures.

### Claim 17

The semiconductor device, comprising:
NMOS and PMOS active regions formed in a substrate;
a gate insulating layer formed on the substrate over the NMOS and PMOS active regions;
a PMOS metal gate structure formed on the gate insulating layer over the PMOS active region and comprising a first metal gate electrode formed from a metal layer and doped with carbon to have a first work function; and,
a NMOS metal gate structure formed on the gate insulating layer over the NMOS active region and comprising a second metal gate electrode formed from the metal layer and having a second work function less than the first work function.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first work function ranges from between about 4.7 to 5.3 eV, and wherein the second work function ranges from between about 3.7 to 4.5 eV.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the metal layer comprises at least one of ruthenium (Ru), zirconium (Zr), niobium (Nb) and tantalum (Ta).

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the metal layer is formed using a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein the PMOS and NMOS metal gate structures further comprise an additional conductive layer formed on the metal layer to define a profile height.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the NMOS and PMOS metal gate structures comprise a stacked structure formed from a patterned portion of the additional conductive layer formed on a patterned portion of the metal layer formed on a patterned portion of the gate insulating layer, and gate spacers formed on sidewalls of the stacked structure.