# US 7,745,879 B2 · Method of fabricating high voltage fully depleted SOI transistor and structure thereof

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- Number: US 7,745,879 B2
- Document ID: US7745879B2
- Status: Granted
- Kind: B2
- Application number: 11/872,953
- Filed: 2007-10-16
- Published: 2009-04-16
- Granted: 2010-06-29
- Earliest claimed: 2007-10-16
- Assignees: International Business Machines Corporation
- Inventors: Andres Bryant; William F. Clark, Jr.; Edward J. Nowak
- Web page: https://patentgrep.com/patent/US7745879B2

## CPC

- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6708: {for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI.

## Claims

### Claim 1

A high voltage fully depleted silicon-on-insulator (SOI) transistor, comprising:
a SOI layer, disposed on an oxide layer of a substrate, the SOI layer having a region including a source region and a ballasted drain region separated by a channel therein;
a gate structure disposed above the channel, wherein the gate structure comprises a gate and a spacer disposed on sidewalls of the gate; and
at least one carrier recombination element disposed above the source region and abutting the gate structure, wherein the at least one carrier recombination element suppresses minority carrier current to prevent a parasitic bipolar effect from occurring during operation of the transistor, wherein the at least one carrier recombination element is physically and electrically connected to the channel, wherein the at least one carrier recombination element has a top surface having a portion embedded underneath the spacer disposed above the source region and a side surface disposed entirely against the spacer disposed above the source region.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the region is of a reduced thickness with respect to a remaining portion of the SOI layer.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the region is of a thickness of less than approximately 300 Å.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the at least one carrier recombination element is a Schottky tab.