# US 7,745,877 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 7,745,877 B2
- Document ID: US7745877B2
- Status: Granted
- Kind: B2
- Application number: 11/901,172
- Filed: 2007-09-13
- Published: 2009-05-07
- Granted: 2010-06-29
- Earliest claimed: 2006-09-15
- Assignees: Ricoh Company, Ltd.
- Inventors: Kikuo Saka; Kimihiko Yamashita; Toshiyuki Takemori; Yuji Watanabe
- Web page: https://patentgrep.com/patent/US7745877B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 72/926: {Multiple bond pads having different sizes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

## Claims

### Claim 1

A semiconductor device provided with a power MOSFET comprising:
a semiconductor substrate constituting a drain;
a trench formed on a surface of the semiconductor substrate;
a gate electrode in the trench, the gate electrode being made of polysilicon and formed via a gate insulating film;
a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench;
a source diffusion layer on the surface of the semiconductor substrate, the source diffusion layer being positioned adjacently to the trench and the body diffusion layer and formed shallower than the body diffusion layer;
a first interlayer insulating film formed on the gate electrode; and
a source electrode film made of a metallic material and formed on the semiconductor substrate including an area on the first interlayer insulating film, the source electrode film being insulated from the gate electrode and electrically connected to the body diffusion layer and the source diffusion layer, wherein
a top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate so that a film thickness of the source electrode film increases above the gate electrode, and
a surface portion of the semiconductor substrate for the trench is formed into a tapered shape; wherein the first interlayer insulating film is disposed on the gate electrode and extended to cover a top surface portion of the semiconductor substrate for the trench and a concave portion is disposed an a surface of the first interlayer insulating film, and the metallic material is embedded in the concave portion.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
a portion of the polysilicon of the gate electrode is extended on the semiconductor substrate and a second interlayer insulating film is formed between the first interlayer insulating film and the source electrode film on the polysilicon extended on the semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the first interlayer insulating film includes a silicon nitride film.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a source trench formed above the body diffusion layer and deeper than the source diffusion layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, further comprising:
a contact diffusion layer formed on the body diffusion layer and surrounding a bottom of the source trench.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, further comprising:
a barrier metal formed on an inner wall of the source trench; and
a plug of metallic material embedded in the source trench via the barrier metal.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein said first interlayer insulating film comprises a lower layer of SiO and an upper layer of SiN.