# US 7,745,875 B2 · Method for producing a vertical field effect transistor

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- Number: US 7,745,875 B2
- Document ID: US7745875B2
- Status: Granted
- Kind: B2
- Application number: 12/143,204
- Filed: 2008-06-20
- Published: 2008-11-27
- Granted: 2010-06-29
- Earliest claimed: 2003-10-30
- Assignees: Infineon Technologies AG
- Inventors: Helmut Tews
- Web page: https://patentgrep.com/patent/US7745875B2

## CPC

- H10D 30/0411: {of FETs having floating gates}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/685: {from the channel}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.

## Claims

### Claim 1

A vertical field effect transistor comprising a projection formed on a substrate for forming a channel region of a field effect transistor;
a control electrode region of a control electrode of the field effect transistor formed on mutually opposite sides of the projection;
an insulating region arranged between the control electrode regions and the projection electrically insulating and adjoining the channel region;
a first connection region near the substrate at one end of the channel region;
a second connection region remote from the substrate at the other end of the channel region, the control electrode having a planar interface which lies parallel to a base area of the projection near the substrate;
wherein the control electrode is delimited by the planar interface in at least ninety percent of its region in the direction of normal (N) to the base area, away from the substrate;
at least one charge storage region arranged between an insulating region and a control electrode region;
wherein the charge storage region is contained in a charge storage material having a further planar interface remote from the substrate, said further planar interface lying parallel to the base area of the projection;
wherein the charge storage material is delimited by the further planar interface remote from the substrate at least ninety percent of its region in the direction of the normal (N) to the base area, away from the substrate; and
wherein the control region has been set back further than the charge storage region, or that the control electrode overlaps the change storage region in the direction of normal (N).

### Claim 2 (depends on 1)

The field effect transistor as claimed in claim 1, wherein the control electrode encloses the projection along a closed circulation, or in the charge storage material encloses the projection along a closed circulation.

### Claim 3 (depends on 1)

The field effect transistor as claimed in claim 1, wherein:
the projection and the substrate are formed in monocrystalline fashion;
the insulating region is a region grown on the projection;
the connection region near to the substrate is arranged with a lateral offset with respect to the base area; or
the projection has a minimal dimensioning of less than one hundred nanometers.

### Claim 4 (depends on 1)

The field effect transistor as claimed in claim 1, wherein the control electrode is delimited by the planar interface everywhere or in at least ninety percent of its region in the direction of the normal (N) to the base area, which points away from the substrate.

### Claim 5 (depends on 1)

The field effect transistor as claimed in claim 1, wherein at least one charge storage region is arranged between an insulating region and a control electrode region and by at least one further insulating region which is electrically insulating and is arranged between a charge storage region and a control electrode region.