# US 7,745,873 B2 · Ultra-thin body vertical tunneling transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,745,873 B2
- Document ID: US7745873B2
- Status: Granted
- Kind: B2
- Application number: 12/233,060
- Filed: 2008-09-18
- Published: 2009-01-15
- Granted: 2010-06-29
- Earliest claimed: 2005-08-29
- Assignees: Micron Technology, Inc.
- Inventors: Leonard Forbes
- Web page: https://patentgrep.com/patent/US7745873B2

## CPC

- H10D 12/211: {Gated diodes}
- H10D 8/70: Tunnel-effect diodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A gate structure is formed along the pillar sidewalls and over the body layers. The transistor operates by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.

## Claims

### Claim 1

A vertical transistor device comprising:
a pillar formed on a substrate;
a pair of source regions, having a first conductivity, formed on the substrate and along a lower portion of opposing sidewalls of the pillar;
ultra-thin silicon bodies formed along a remaining portion of the opposing sidewalls and above and in contact with each source region;
a drain region formed over and in contact with the pillar and the silicon bodies wherein the drain region is comprised of an opposite conductivity from the source region;
a gate insulator formed over the pair of source regions, the silicon bodies, and the drain region; and
a gate formed vertically around the gate insulator.

### Claim 2 (depends on 1)

The device of claim 1 wherein the transistor is implemented in 0.1 micron technology.

### Claim 3 (depends on 1)

The device of claim 1 wherein the pillar has a height of 100 nm.

### Claim 4 (depends on 1)

The device of claim 1 wherein the ultra-thin silicon bodies have a thickness in the range of 5-20 nm.

### Claim 5 (depends on 1)

The device of claim 1 wherein the pair of source regions has a p+ conductivity and the drain region has an n+ conductivity.

### Claim 6 (depends on 1)

The device of claim 1 wherein the pillar is an oxide pillar.

### Claim 7

A vertical tunneling, ultra-thin silicon body transistor comprising:
an oxide pillar formed on a silicon substrate;
a p+ source region formed on the substrate and a lower portion of opposing sides of the pillar;
an n+ drain region formed over the top of the pillar;
an ultra-thin silicon body formed along a remaining upper portion of each opposing side of the pillar between the source region and the drain region;
an oxide gate dielectric formed around the pillar and the silicon bodies; and
a gate structure formed over the gate dielectric.

### Claim 8 (depends on 7)

The transistor of claim 7 and further including p+ wires doped into the substrate and coupled to the source region.

### Claim 9 (depends on 7)

The transistor of claim 7 wherein the gate structure is a dual gate.

### Claim 10 (depends on 7)

The transistor of claim 7 wherein the gate structure is a surround gate that is formed around the oxide pillar.

### Claim 11 (depends on 7)

The transistor of claim 7 wherein the gate structure is comprised of a polysilicon.

### Claim 12 (depends on 7)

The transistor of claim 7 wherein the gate structure is configured to induce an n-channel between each source region and the drain region in response to biasing of the gate structure.

### Claim 13

A vertical tunneling, ultra-thin silicon body transistor comprising:
an n-type silicon substrate;
an oxide pillar formed on the substrate;
a p+ source region formed on the substrate and vertically along a lower portion of sidewalls of the pillar;
a lightly doped, p-type silicon body formed around the oxide pillar;
an n+ drain region formed in a silicon layer on top of the pillar and the silicon body;
a gate insulator formed around the pillar and over the silicon body, drain region, and source region; and
a surrounding gate structure formed over the gate insulator.

### Claim 14 (depends on 13)

The transistor of claim 13 wherein the gate structure is comprised of polysilicon and the gate insulator is comprised of an oxide.

### Claim 15 (depends on 13)

The transistor of claim 13 wherein the silicon body is formed to a thickness in the range of 5-20 nm, the transistor is formed to a height of 100 nm and a thickness in the range of 25-50 nm.

### Claim 16 (depends on 13)

The transistor of claim 13 wherein the transistor is formed in an n-well of the silicon substrate.

### Claim 17 (depends on 13)

The transistor of claim 13 wherein the silicon body is formed around a remaining portion of the pillar and between and in contact with the drain region and the source region.

### Claim 18 (depends on 13)

The transistor of claim 13 and further including a metal connection coupled to the drain region at the top of the pillar.