# US 7,745,871 B2 · Fin field effect transistors including oxidation barrier layers

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- Number: US 7,745,871 B2
- Document ID: US7745871B2
- Status: Granted
- Kind: B2
- Application number: 11/871,453
- Filed: 2007-10-12
- Published: 2008-02-07
- Granted: 2010-06-29
- Earliest claimed: 2004-06-04
- Inventors: Chang-Woo Oh; Dong-Gun Park; Dong-Won Kim; Yong-Kyu Lee
- Web page: https://patentgrep.com/patent/US7745871B2

## CPC

- H10D 30/6213: {having rounded corners}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

## Claims

### Claim 1

A semiconductor device, comprising:
a fin-shaped active region vertically protruding from a semiconductor substrate, the fin-shaped active region having at least one curved sidewall portion proximate an upper surface of the fin-shaped active region;
an oxide layer on opposing sidewalls of the fin-shaped active region;
a capping oxide layer on the upper surface of the fin-shaped active region, the capping oxide layer being thicker than the oxide layer; and
an oxidation barrier layer extending along opposing sidewalls of the fin-shaped active region, wherein the oxidation barrier layer has a curved upper portion proximate the upper surface of the fin-shaped active region, wherein the curved upper portion faces the opposing sidewalls of the fin-shaped active region and facilitates oxidation at the upper surface of the fin-shaped active region.

### Claim 2 (depends on 1)

The device of claim 1, wherein the oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the upper surface and a base of the fin-shaped active region.

### Claim 3 (depends on 1)

The device of claim 1, wherein the fin-shaped active region has a second curved sidewall portion proximate the base of the fin-shaped active region that is spaced apart from the at least one curved sidewall portion proximate the upper surface of the fin-shaped active region such that a width of the base of the fin-shaped active region is narrower than a width at upper portions of the fin-shaped active region.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
a gate electrode formed on the oxide layer and on the capping layer.

### Claim 5 (depends on 1)

The device of claim 1, further comprising:
a charge storage layer on the oxide layer on the sidewalls of the fin-shaped active region;
a blocking insulating layer on the charge storage layer and on the capping oxide layer; and
a gate electrode on the blocking insulating layer.

### Claim 6 (depends on 5)

The device of claim 5, wherein the charge storage layer comprises silicon nitride, polysilicon, amorphous silicon, nano-crystal, and/or quantum dot materials.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
an oxidation barrier spacer on the oxide layer formed on the sidewalls of the fin-shaped active region;
a blocking insulating layer on the oxidation barrier spacer and on the capping oxide layer; and
a gate electrode on the blocking insulating layer,
wherein the oxidation barrier spacer comprises silicon nitride.

### Claim 8 (depends on 1)

The device of claim 1, wherein the capping oxide layer has a dielectric constant lower than a nitride mask pattern.