# US 7,745,870 B2 · Programming and erasing structure for a floating gate memory cell and method of making

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- Number: US 7,745,870 B2
- Document ID: US7745870B2
- Status: Granted
- Kind: B2
- Application number: 11/626,681
- Filed: 2007-01-24
- Published: 2007-05-24
- Granted: 2010-06-29
- Earliest claimed: 2004-09-17
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Gowrishankar L. Chindalore; Craig T. Swift
- Web page: https://patentgrep.com/patent/US7745870B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

## Claims

### Claim 1

A floating gate device a substrate, comprising:
a substrate;
a gate dielectric overlying the substrate;
a floating gate having a first floating gate portion and a second floating gate portion; wherein:
the first floating gate portion overlies the gate dielectric, wherein the first floating gate portion is continuous;
the second floating gate portion overlies the first floating gate portion, wherein the second floating gate portion includes a plurality of separate portions over the first floating gate portion;
an etch stop layer between each of the plurality of separate portions of the second floating gate portion and the first floating gate portion that permits passage of charge during programming and erasing of the floating gate device;
an interlevel dielectric overlying the separate portions of the second floating gate portion and the first floating gate portion; and
a control gate overlying the interlevel dielectric, wherein the control gate extends down in a region between the separate portions and over the first floating gate portion.

### Claim 2 (depends on 1)

A floating gate device of claim 1, wherein the substrate further comprises isolation regions, and wherein the plurality of separate portions of the second floating gate portion are between isolation regions and the region between the separate portions is between the isolation regions.

### Claim 3 (depends on 2)

A floating gate device of claim 2, wherein at least one of the plurality of separate portions of the second floating gate portion is adjacent a sidewall of an isolation region.

### Claim 4 (depends on 1)

A floating gate device of claim 1, wherein the etch stop layer is substantially electrically transparent between each of the plurality of separate portions of the second floating gate portion and the first floating gate portion.

### Claim 5 (depends on 1)

A floating gate device of claim 1, wherein the etch stop layer has a thickness in a range of approximately 15 to 20 Angstroms.