# US 7,745,864 B2 · Semiconductor device with contact stabilization between contact plugs and bit lines and method for manufacturing the same

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- Number: US 7,745,864 B2
- Document ID: US7745864B2
- Status: Granted
- Kind: B2
- Application number: 11/953,313
- Filed: 2007-12-10
- Published: 2009-04-09
- Granted: 2010-06-29
- Earliest claimed: 2007-10-09
- Assignees: Hynix Semiconductor Inc.
- Inventors: Dong Chul Koo
- Web page: https://patentgrep.com/patent/US7745864B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/485: {Bit line contacts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate divided into a cell array region, a core region, and a peripheral region;
bit lines formed over the substrate in the respective regions; an interlayer dielectric formed so as to cover the bit lines in the respective regions, the interlayer dielectric including grooves formed around the bit lines in the core region and the peripheral region; storage node contact plugs formed in the cell array region; blocking patterns formed around the bit lines in the core region and the peripheral region, the blocking patterns comprising a layer filled in the grooves of the interlayer dielectric for blocking formation of the metal contact plugs below the blocking patterns;
capacitors formed in the cell array region to come into contact with the storage node contact plugs; and
the metal contact plugs formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the storage node contact plugs have a single-layered structure.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the storage node contact plugs have a stacked layer structure including a lower pattern and an upper pattern.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the blocking patterns are formed in the same layer as the upper patterns of the storage node contact plugs.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein a sectional shape of the blocking patterns is one of a ring, a picture frame, a bar, and a ‘U’ rotated clockwise by 90°.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the blocking patterns have a width in the range of 0.001˜0.5 μm.

### Claim 7

A method for manufacturing a semiconductor device, comprising the steps of:
forming bit lines in a cell array region, a core region, and a peripheral region of a semiconductor substrate; forming an interlayer dielectric covering the bit lines in the respective regions, and forming grooves in the interlayer dielectric around the bit lines in the core region and the peripheral region; forming storage node contact plugs in the cell array region, and forming blocking patterns around the bit lines of the core region and the peripheral regions, wherein the forming the blocking patterns comprises filling the grooves with a layer so as to form the blocking patterns for blocking formation of metal contact plugs below the blocking patterns;
forming capacitors in the cell array region to come into contact with the storage node contact plugs; and
forming the metal contact plugs to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the storage node contact plugs are formed simultaneously with the blocking patterns, and the blocking patterns are formed in a single-layered structure.

### Claim 9 (depends on 7)

The method according to claim 7, wherein the storage node contact plugs are formed simultaneously with the blocking patterns, and the blocking patterns are formed in a stacked layer structure including a lower pattern formed in a lower layer and an upper pattern formed in an upper layer.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the blocking patterns are formed in the upper layer, and are formed simultaneously with the upper patterns of the storage node contact plugs.

### Claim 11 (depends on 7)

The method according to claim 7, wherein the blocking patterns are formed to have the sectional shape of a ring, a picture frame, a bar, or a ‘U’ rotated clockwise by 90°.

### Claim 12 (depends on 7)

The method according to claim 7, wherein the blocking patterns are formed to have a width in the range of 0.001˜0.5 μm.