# US 7,745,863 B2 · Flip FERAM cell and method to form same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,745,863 B2
- Document ID: US7745863B2
- Status: Granted
- Kind: B2
- Application number: 12/146,576
- Filed: 2008-06-26
- Published: 2008-10-23
- Granted: 2010-06-29
- Earliest claimed: 1999-08-26
- Assignees: International Business Machines Corporation
- Inventors: James W. Adkisson; Charles Thomas Black; Alfred Grill; Randy William Mann; Deborah Ann Neumayer; Wilbur David Pricer; Katherine Lynn Saenger; Thomas McCarroll Shaw
- Web page: https://patentgrep.com/patent/US7745863B2

## CPC

- H10D 1/682: {having dielectrics comprising perovskite structures}
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B 53/30: characterised by the memory core region
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- Y10S 438/977: Thinning or removal of substrate
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

## Claims

### Claim 1

A FE delivery wafer comprising a carrier substrate, a sacrificial release layer located directly on a surface of said carrier substrate, a first conductive layer located directly on a surface of said sacrificial release layer, a ferroelectric layer located on a surface of said first conductive layer, and a second conductive layer that is located on a surface of said ferroelectric layer and is also located on an outermost surface of said FE delivery wafer.

### Claim 2 (depends on 1)

The FE delivery wafer of claim 1 wherein said carrier substrate is a semiconducting material or a dielectric material.

### Claim 3 (depends on 2)

The FE delivery wafer of claim 2 wherein said semiconducting material is Si, Ge, SiGe, GaAs, InAs, InP, another III/V compound or an organic semiconductor.

### Claim 4 (depends on 2)

The FE delivery wafer of claim 2 wherein said dielectric material is an inorganic or organic dielectric material selected from the group consisting of SiO2, Si3N4, SiCOH, diamond-like carbon, paralyene polymers, polyimides and silicon-containing polymers, organic polymers, and hybrid organo-silicon polymers (HOSP).

### Claim 5 (depends on 1)

The FE delivery wafer of claim 1 wherein said sacrificial release layer is selected from the group consisting of GeO2, W, TiN, IrO2, PdO and WSi2.

### Claim 6 (depends on 5)

The FE delivery wafer of claim 5 wherein said sacrificial release layer is provided by implanting said delivery wafer with a desorbable species prior to or after deposition.

### Claim 7 (depends on 6)

The FE delivery wafer of claim 6 wherein said desorbable species is hydrogen.

### Claim 8 (depends on 1)

The FE delivery wafer of claim 1 wherein said first conductive layer does not contact said carrier substrate.

### Claim 9 (depends on 1)

The FE delivery wafer of claim 1 wherein said second conductive layer is located directly on a surface of said ferroelectric layer.

### Claim 10 (depends on 9)

The FE delivery wafer of claim 9 wherein said first conductive layer does not contact said carrier substrate.

### Claim 11 (depends on 10)

The FE delivery wafer of claim 10 wherein said second conductive layer does not contact said first conductive layer.

### Claim 12 (depends on 11)

The FE delivery wafer of claim 11 wherein said second conductive layer does not contact said sacrificial release layer.

### Claim 13 (depends on 12)

The FE delivery wafer of claim 12 wherein said second conductive layer does not contact said carrier substrate.

### Claim 14

A FE delivery wafer comprising a carrier substrate, a sacrificial release layer located directly on a surface of said carrier substrate, a first conductive layer located on a surface of said sacrificial release layer, a ferroelectric layer located on a surface of said first conductive layer and not contacting said carrier substrate, and a second conductive layer that is located on a surface of said ferroelectric layer and is also located on an outermost surface of said FE delivery wafer.

### Claim 15 (depends on 14)

The FE delivery wafer of claim 14 wherein said first conductive layer is located directly on said surface of said sacrificial release layer.