# US 7,745,847 B2 · Metal oxide semiconductor transistor

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- Number: US 7,745,847 B2
- Document ID: US7745847B2
- Status: Granted
- Kind: B2
- Application number: 11/836,772
- Filed: 2007-08-09
- Published: 2009-02-12
- Granted: 2010-06-29
- Earliest claimed: 2007-08-09
- Assignees: United Microelectronics Corp.
- Inventors: Chu-Yin Tseng; Shih-Chieh Hsu; Chih-Chiang Wu; Shyh-Fann Ting; Po-Lun Cheng; Hsuan-Hsu Chen
- Web page: https://patentgrep.com/patent/US7745847B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed in the semiconductor substrate adjacent to the gate, and then an epitaxial layer is formed in the recess. A lightly doped region is formed in the semiconductor substrate adjacent to the gate. Finally, a spacer is formed on the sidewall of the gate.

## Claims

### Claim 1

A MOS transistor structure, comprising:
a gate formed on a semiconductor substrate;
two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate;
a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate; and
two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the gate further comprises:
a dielectric layer;
a conductive layer, positioned on the dielectric layer; and
a cap layer, positioned on the conductive layer.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the MOS transistor comprises a PMOS transistor.

### Claim 4 (depends on 3)

The structure of claim 3, wherein the epitaxial layer comprises SiGe.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the MOS transistor comprises an NMOS transistor.

### Claim 6 (depends on 5)

The structure of claim 5, wherein the epitaxial layer comprises SiC.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the spacer further comprises an offset spacer, positioned between the gate and the spacer.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the spacer further comprises an oxide liner and a nitride spacer.

### Claim 9 (depends on 1)

The structure of claim 1, wherein the edge of the raised epitaxial layers is not aligned with the edge of the spacer.

### Claim 10 (depends on 1)

The structure of claim 1, wherein the spacer further comprises a L-shaped spacer.

### Claim 11 (depends on 1)

The structure of claim 1, further comprising a lightly doped drain disposed in the semiconductor substrate and outside the raised epitaxial layers.