# US 7,745,812 B2 · Integrated circuit including vertical diode

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- Number: US 7,745,812 B2
- Document ID: US7745812B2
- Status: Granted
- Kind: B2
- Application number: 11/766,231
- Filed: 2007-06-21
- Published: 2008-12-25
- Granted: 2010-06-29
- Earliest claimed: 2007-06-21
- Assignees: Qimonda North America Corp.
- Inventors: Thomas Happ; Jan Boris Philipp
- Web page: https://patentgrep.com/patent/US7745812B2

## CPC

- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

An integrated circuit includes a vertical diode defined by crossed line lithography.

## Claims

### Claim 1

An integrated circuit comprising:
a vertical diode;
a silicide contact contacting the vertical diode;
a first electrode coupled to the silicide contact;
a spacer having a first sidewall contacting a first sidewall of the first electrode;
a resistivity changing material coupled to the first electrode; and
a second electrode coupled to the resistivity changing material,
wherein a second sidewall of the spacer is aligned on a line with a sidewall of the vertical diode and a second sidewall of the first electrode.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the first electrode comprises an etch stop material layer contacting the spacer.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the first electrode comprises a first electrode material contacting the silicide contact and a second electrode material contacting the resistivity changing material.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, further comprising:
an N+ word line coupled to the diode.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the resistivity changing material comprises phase change material.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, further comprising:
at least one encapsulation material layer encapsulating the resistivity changing material and the second electrode.

### Claim 7

An integrated circuit comprising:
a vertical diode including a first polarity region and a second polarity region;
a silicide contact contacting the second polarity region;
a first electrode coupled to the silicide contact;
a spacer having a first sidewall contacting a first sidewall of the first electrode;
a phase change element coupled to the first electrode; and
a second electrode coupled to the phase change element,
wherein a second sidewall of the spacer is aligned on a line with a second sidewall of the first electrode and a sidewall of the vertical diode.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, further comprising:
a word line contacting the first polarity region; and
a bit line coupled to the second electrode.

### Claim 9

An integrated circuit comprising:
a first polarity region;
a second polarity region contacting the first polarity region;
a silicide contact contacting the second polarity region;
a first electrode coupled to the silicide contact;
a spacer having a first sidewall contacting a first sidewall of the first electrode;
a resistive memory element coupled to the first electrode; and
a second electrode coupled to the resistive memory element,
wherein a second sidewall of the spacer is aligned on a line with a second sidewall of the first electrode, a sidewall of the silicide contact, a sidewall of the second polarity region, and a sidewall of the first polarity region.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the first electrode comprises an etch stop material layer contacting the spacer.

### Claim 11 (depends on 9)

The integrated circuit of claim 9, wherein the first electrode comprises a first electrode material contacting the silicide contact and a second electrode material contacting the resistive memory element.

### Claim 12 (depends on 9)

The integrated circuit of claim 9, wherein the first polarity region comprises an N− region, and
wherein the second polarity region comprises a P+ region.

### Claim 13 (depends on 9)

The integrated circuit of claim 9, further comprising:
an N+ word line contacting the N− region, the N+ word line having a sidewall self-aligned with the second sidewall of the spacer.

### Claim 14 (depends on 9)

The integrated circuit of claim 9, further comprising:
at least one encapsulation material layer encapsulating the resistive memory element and the second electrode.

### Claim 15 (depends on 9)

The integrated circuit of claim 9, wherein the resistive memory element comprises a phase change element.

### Claim 16

An integrated circuit comprising:
a vertical diode;
a silicide contact contacting the vertical diode;
a first electrode coupled to the silicide contact, the first electrode having a first sidewall aligned in a line with a first sidewall of the silicide contact; and the first electrode having a second sidewall aligned in a line with a second sidewall of the silicide contact;
a spacer having a first sidewall contacting a third sidewall of the first electrode;
a resistivity changing material coupled to the first electrode; and
a second electrode coupled to the resistivity changing material,
wherein a second sidewall of the spacer is aligned on a line with a sidewall of the vertical diode and the second sidewall of the first electrode.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the first electrode comprises an etch stop material layer contacting the spacer, the etch stop material layer having a first sidewall aligned in a line with the first sidewall of the silicide contact, and the etch stop material layer having a second sidewall aligned in a line with the second sidewall of the silicide contact.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the first electrode comprises a first electrode material contacting the silicide contact and a second electrode material contacting the resistivity changing material.

### Claim 19 (depends on 16)

The integrated circuit of claim 16, further comprising:
an N+ word line coupled to the diode.

### Claim 20 (depends on 16)

The integrated circuit of claim 16, wherein the resistivity changing material comprises phase change material.

### Claim 21 (depends on 16)

The integrated circuit of claim 16, further comprising:
at least one encapsulation material layer encapsulating the resistivity changing material and the second electrode; and
a dielectric material laterally surrounding the encapsulation material layer.

### Claim 22 (depends on 16)

The integrated circuit of claim 16, further comprising:
a dielectric material laterally surrounding the vertical diode, the silicide contact, the first electrode, and the spacer.