# US 7,745,808 B2 · Differential negative resistance memory

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- Number: US 7,745,808 B2
- Document ID: US7745808B2
- Status: Granted
- Kind: B2
- Application number: 12/003,573
- Filed: 2007-12-28
- Published: 2008-06-05
- Granted: 2010-06-29
- Earliest claimed: 2003-04-10
- Assignees: Micron Technology, Inc.
- Inventors: Kristy A. Campbell
- Web page: https://patentgrep.com/patent/US7745808B2

## CPC

- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- H10N 70/026: {by physical vapor deposition, e.g. sputtering}
- H10N 70/046: {by diffusion, e.g. photo-dissolution}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/8825: {Selenides, e.g. GeSe}
- G11C 2211/5614: Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to a device in accordance with the invention can maintain its memory for a matter of minutes, hours, or days before a refresh is necessary. The power requirements of the device are far reduced compared to DRAM. The memory function of the device is highly stable, repeatable, and predictable. The device can be produced in a variety of ways.

## Claims

### Claim 1

A differential negative resistance memory device, comprising:
a substrate;
a first conductive layer over said substrate;
a first germanium selenide layer over said first conductive layer;
a silver selenide layer over said first germanium selenide layer;
a second germanium selenide layer over said silver selenide layer, wherein said first and second germanium selenide layers have a chemical formula GexSe100-x, x being in the range of about 18-43;
a silver layer over said second germanium selenide layer; and
a second conductive layer over said silver layer;
wherein at least said first germanium selenide layer is configured to exhibit a differential negative resistance memory such that it is programmable to a higher current flow read state and a lower current flow read state in response to applied first and second programming voltages, respectively.

### Claim 2 (depends on 1)

The differential negative resistance memory device of claim 1, wherein differential negative resistance memory is semi-volatile.

### Claim 3 (depends on 1)

The differential negative resistance memory device of claim 1, wherein a current flow read state programmed to said memory device is maintained for at least a minute without refreshing.

### Claim 4 (depends on 1)

The differential negative resistance memory device of claim 1, wherein said higher current flow read state is increased relative to a non-programmed current amplitude at a read voltage.

### Claim 5 (depends on 1)

The differential negative resistance memory device of claim 1, wherein said lower current flow read state is decreased relative to a non-programmed current amplitude at a read voltage.

### Claim 6

A processor system, comprising;
a processor;
a differential negative resistance memory device, said memory device comprising;
a first electrode and a second electrode; and
a resistance variable region separating said first and second electrodes and in electrical communication therewith, said resistance variable region being configured so as to exhibit differential negative resistance memory behavior as storing at least one memory state as a read current in response to an applied voltage.

### Claim 7 (depends on 6)

The processor system of claim 6, wherein said memory device can be programmed to a first read current state upon application of a first voltage potential and to a second read current state upon application of a second voltage potential.

### Claim 8 (depends on 6)

The processor system of claim 6, wherein said at least one memory state is semi-volatile.

### Claim 9 (depends on 6)

The processor system of claim 6, wherein said at least one memory state written to said memory device is retained for at least a minute without refreshing.

### Claim 10 (depends on 7)

The processor system of claim 7, wherein said first read current state is increased relative to a non-programmed read current at a read voltage.

### Claim 11 (depends on 7)

The processor system of claim 7, wherein said second read current state is decreased relative to a non-programmed read current at a read voltage.