# US 7,745,773 B1 · Multi-color CMOS pixel sensor with shared row wiring and dual output lines

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- Number: US 7,745,773 B1
- Document ID: US7745773B1
- Status: Granted
- Kind: B1
- Application number: 12/101,879
- Filed: 2008-04-11
- Granted: 2010-06-29
- Earliest claimed: 2008-04-11
- Assignees: Foveon, Inc.
- Inventors: Richard B. Merrill
- Web page: https://patentgrep.com/patent/US7745773B1

## CPC

- H04N 25/771: comprising storage means other than floating diffusion
- H04N 25/70: SSIS architectures; Circuits associated therewith
- H04N 25/766: comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels}
- H04N 23/84: for processing colour signals
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

An array of multicolor CMOS pixel sensors has a plurality of photosensors per pixel, each photosensor coupled to a single sense node through a select transistor having a select input, each pixel sensor including a reset transistor coupled to the sense node and having a reset input, an amplifier coupled to the sense node and a row-select transistor coupled to the amplifier. The select inputs and the reset inputs for pixel sensors in a pair of adjacent rows are coupled to select signal lines and reset signal lines associated with the pair of rows. The amplifier transistors in individual columns of each row are coupled to a column output line through a row-select transistor having a row-select input. The row-select inputs for pixel sensors in each row of the array are coupled to a row-select line associated with the row.

## Claims

### Claim 1

An array of CMOS pixel sensors, each pixel sensor associated with a row and a column of the array and having a plurality of photosensors per pixel location, each photosensor coupled to a single sense node through a select transistor having a select input, each pixel sensor including a reset transistor coupled to the sense node and having a reset input, an amplifier transistor coupled to the sense node and a row-select transistor coupled to the amplifier, wherein:
the select inputs for pixel sensors in a pair of adjacent rows are coupled to select signal lines associated with only that pair of rows;
the reset inputs for pixel sensors in each row is coupled to reset signal lines associated with that row;
the amplifier transistors in individual columns of each row are coupled to a column output line through a row-select transistor having a row-select input; and
the row-select inputs for pixel sensors in each row of the array are coupled to a row-select line associated with the row.

### Claim 2 (depends on 1)

The array of claim 1 wherein the select signal lines, the reset signal lines and the row-select lines run in a row direction of the array and the column output line runs in a column direction of the array.

### Claim 3 (depends on 2)

The array of claim 2 wherein the amplifier in each pixel sensor is a source-follower transistor having its drain coupled to a source-follower drain potential node, the source-follower drain potential node for each pixel sensor in a row in the array coupled to a source-follower drain potential line and running in the column direction of the array.

### Claim 4 (depends on 2)

The array of claim 2 wherein the amplifier in each pixel sensor is a source-follower transistor having its drain coupled to a source-follower drain potential node, the source-follower drain potential node for each pixel sensor in a row in the array coupled to a source-follower drain potential line associated with that row and running in the row direction of the array.