# US 7,745,343 B1 · Method for fabricating semiconductor device with fuse element

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- Number: US 7,745,343 B1
- Document ID: US7745343B1
- Status: Granted
- Kind: B1
- Application number: 12/431,643
- Filed: 2009-04-28
- Granted: 2010-06-29
- Earliest claimed: 2009-02-12
- Assignees: Vanguard International Semiconductor Corporation
- Inventors: Wen-Hsun Lo; Hsing-Chao Liu; Jin-Dong Chern; Kwang-Ming Lin
- Web page: https://patentgrep.com/patent/US7745343B1

## CPC

- H10W 20/494: {changeable by the use of an external beam, e.g. laser beam or ion beam}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequentially formed. A bond pad is formed over the second interlayer dielectric layer in a second device region of the semiconductor structure. A passivation layer is formed over the bond pad and the second interlayer dielectric layer. A first etching process is performed to form a first opening in the first device region and a second opening in the second device region, wherein the first opening exposes a portion of the second interlayer dielectric layer over the fuse element and, and the second opening partially exposes a portion of the bond pad. A second etching process and a third etching process are performed to leave another passivation layer conformably covering the fuse element and the semiconductor structure adjacent thereto.

## Claims

### Claim 1

A method for fabricating a semiconductor device with a fuse element, comprising:
providing a semiconductor structure having a first device region and a second device region;
forming a fuse element over the semiconductor structure in the first device region;
forming a first interlayer dielectric layer, conformably covering the fuse element and the semiconductor structure;
forming an etching stop layer, conformably covering the first interlayer dielectric layer;
forming a second interlayer dielectric layer, blanketly covering the etching stop layer, wherein the second interlayer dielectric layer is formed with a planar top surface;
forming a bond pad over the second interlayer dielectric layer in the second device region;
forming a passivation layer, conformably covering the bond pad and the second interlayer dielectric layer;
performing a first etching process to pattern the passivation layer, respectively forming a first opening in the first device region and a second opening in the second device region, wherein the first opening is substantially located over the fuse element and exposes a portion of the second interlayer dielectric layer, and the second opening is substantially located over the bond pad and partially exposes a portion of the bond pad;
performing a second etching process, removing the portion of the second interlayer dielectric layer exposed by the first opening and exposing a top surface and partial sidewalls of the etching stop layer formed over the fuse element; and
performing a third etching process, removing the portion of the second interlayer dielectric layer, the etching stop layer, and a portion of the first interlayer dielectric layer exposed by the first opening such that another passivation layer conformably covering the fuse element and the semiconductor structure adjacent to the fuse element is left.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the first and second interlayer dielectric layers comprise silicon oxide, the passivation layer comprises silicon nitride, and the etching stop layer comprises silicon oxynitride.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the first etching process is a dry etching process utilizing etching gases comprising CF4, CHF3, SF6 and Ar.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the second etching process is a dry etching process utilizing etching gases comprising C4F8, CHF3, Ar and O2.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the third etching process is a dry etching process utilizing etching gases comprising CF4, CHF3, Ar and O2.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein after the second etching process, a residue portion of the first interlayer dielectric layer is left at the sidewalls of the etch stop layer, and the residue portion of the first interlayer dielectric layer is apart from the first interlayer dielectric layer adjacent to the first opening in a distance of about 2000-6000 Å.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein after the third etching process, the another passivation layer conformably covering the fuse element and the semiconductor structure adjacent to the fuse element has a thickness of about 0-5000 Å over the top surface of the fuse structure and a thickness of about 2000-6000 Å over the surface of the semiconductor structure.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein the fuse element comprises aluminum.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein the fuse element comprises aluminum-copper alloy and titanium nitride.

### Claim 10 (depends on 1)

The method as claimed in claim 1, wherein the bond pad comprises aluminum.

### Claim 11 (depends on 1)

The method as claimed in claim 1, wherein the bond pad comprises aluminum-copper alloy and titanium nitride.