# US 7,745,341 B2 · Phase-change semiconductor device and methods of manufacturing the same

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- Number: US 7,745,341 B2
- Document ID: US7745341B2
- Status: Granted
- Kind: B2
- Application number: 11/482,760
- Filed: 2006-07-10
- Published: 2007-01-18
- Granted: 2010-06-29
- Earliest claimed: 2005-07-12
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Tae-Won Kim; Yong-Sun Ko; Ki-Jong Park; Kyung-Hyun Kim
- Web page: https://patentgrep.com/patent/US7745341B2

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

## Claims

### Claim 1

A method of manufacturing a phase-change semiconductor device, comprising:
forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate;
forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold;
forming an oxide layer pattern on the etch stop layer to at least partially fill the opening;
forming an insulation layer on the etch stop layer and the oxide layer pattern;
forming a contact hole through the insulation layer and the etch stop layer to expose a portion of the metal layer pattern;
forming a contact electrode to fill the contact hole, the contact electrode being electrically connected to the metal layer pattern;
forming a phase-change layer on the insulation layer and the contact electrode;
forming an upper electrode layer on the phase-change layer; and
partially etching the upper electrode layer and the phase-change layer to form a phase-change layer pattern and an upper electrode.

### Claim 2 (depends on 1)

The method of claim 1, wherein the upper thickness threshold is about 3,000 Å.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the metal layer pattern includes:
forming a metal layer on the substrate;
forming a photoresist pattern on the metal layer, the photoresist pattern exposing a portion of the metal layer;
partially removing the metal layer using the photoresist pattern as an etching mask to form the metal layer pattern including the opening that exposes the portion of the substrate; and
reducing the photoresist pattern.

### Claim 4 (depends on 1)

The method of claim 1, wherein the etch stop layer includes at least one of silicon nitride, silicon oxynitride, and silicon-rich silicon oxide.

### Claim 5 (depends on 1)

The method of claim 1, wherein the etch stop layer includes silicon-rich silicon oxide having a content of silicon greater than that of the oxide layer pattern.

### Claim 6 (depends on 1)

The method of claim 1, wherein the etch stop layer has a thickness between about 100 Å to about 2,000 Å.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the oxide layer pattern includes:
forming an oxide layer to at least partially fill the opening and to cover the etch stop layer; and
performing a planarization process on the oxide layer until an upper face of the etch stop layer formed on the metal layer pattern is exposed.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a spacer on a sidewall of the contact hole.

### Claim 9

A method of manufacturing a phase-change semiconductor device, comprising:
forming a metal layer on a substrate;
forming an etch stop layer on the metal layer, the etch stop layer having a thickness less than an upper thickness threshold;
forming a photoresist pattern on the etch stop layer;
etching the etch stop layer and the metal layer using the photoresist pattern to form an etch stop layer pattern and a metal layer pattern on the substrate and to form an opening exposing a portion of the substrate;
reducing the photoresist pattern;
forming an oxide layer pattern to at least partially fill the opening;
forming an insulation layer on the etch stop layer pattern and the oxide layer pattern;
forming a contact hole through the insulation layer and the etch stop layer, the contact hole exposing a portion of the metal layer pattern;
forming a contact electrode to fill the contact hole, the contact electrode being electrically connected to the metal layer pattern;
forming a phase-change layer on the insulation layer, the phase-change layer being electrically connected to the contact electrode;
forming an upper electrode layer on the phase-change layer; and
partially etching the upper electrode layer and the phase-change layer to form a phase-change layer pattern and an upper electrode.

### Claim 10 (depends on 9)

The method of claim 9, wherein the etch stop layer includes at least one of silicon nitride, silicon oxynitride and silicon-rich silicon oxide.

### Claim 11 (depends on 9)

The method of claim 9, wherein the upper thickness threshold is about 3,000 Å.

### Claim 12 (depends on 9)

The method of claim 9, wherein the etch stop layer has a thickness between about 100 Å to about 2,000 Å.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the oxide layer pattern includes:
forming an oxide layer to fill the opening and to cover the etch stop layer; and
performing a planarization process on the oxide layer until an upper face of the etch stop layer is exposed.

### Claim 14 (depends on 9)

The method of claim 9, further comprising:
forming a spacer on a sidewall of the contact hole.