# US 7,745,335 B2 · Semiconductor device manufactured by reducing hillock formation in metal interconnects

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- Number: US 7,745,335 B2
- Document ID: US7745335B2
- Status: Granted
- Kind: B2
- Application number: 11/614,511
- Filed: 2006-12-21
- Published: 2008-06-26
- Granted: 2010-06-29
- Earliest claimed: 2006-12-21
- Assignees: Texas Instruments Incorporated
- Inventors: Ju-Ai Ruan; Changming Jin; Sopa Chevacharoenkul; Satyavolu Papa Rao; Tae Seung Kim
- Web page: https://patentgrep.com/patent/US7745335B2

## CPC

- H10P 70/277: {the processing being a planarisation of conductive layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- Y10S 438/937: Hillock prevention
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

## Claims

### Claim 1

A method of fabricating an integrated circuit, including the fabrication of an interconnect using a damascene process, the method comprising:
forming a pre-metal dielectric layer over a semiconductor device formed on a substrate;
forming a contact for electrical connection to the device through the pre-metal dielectric layer;
forming an inter-layer dielectric layer over the pre-metal dielectric layer and the contact;
forming an interconnect opening in the inter-level dielectric layer by etching through a patterned mask down to the contact;
forming a metal layer over the inter-level dielectric layer and filling the interconnect opening;
performing a planarization process to remove at least a portion of the metal layer from over the inter-level dielectric layer;
pre-charging a reaction chamber of a plasma deposition tool without the substrate in the chamber, by generating a first reactive species from a first source gas in the presence of a first plasma at a first temperature; the first source gas including NH3 and the first temperature being higher than 400° C.;
following planarization, introducing the substrate into the pre-charged chamber, with the first plasma terminated and the first reactive species still present in the chamber;
with the substrate introduced into the pre-charged chamber, treating the substrate with a second reactive species from a second source gas in the presence of a second plasma at a second temperature; the second source gas including NH3 and He, the second temperature being lower than 400° C., and the second reactive species being started while the first reactive species is still present in the chamber; and
with the substrate still in the chamber, depositing a layer of silicon carbon nitride over a remaining portion of the metal layer using a third source gas including silicon and carbon components.

### Claim 2 (depends on 1)

The method of claim 1, further comprising removing the substrate from the chamber following depositing the layer of silicon carbon nitride; and cleaning the chamber to remove deposits from interior surfaces of the chamber.

### Claim 3 (depends on 2)

The method of claim 2, further comprising, following the cleaning, seasoning the chamber by depositing silicon carbon nitride on the interior surfaces.

### Claim 4 (depends on 2)

The method of claim 2, wherein the chamber is cleaned using a cleaning gas containing fluorine and oxygen.

### Claim 5 (depends on 1)

The method of claim 1, wherein the time between terminating the first plasma and introducing the substrate into the pre-charged chamber is 60 seconds or less.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gas having silicon and carbon components comprises trimethylsilane.

### Claim 7

A method of fabricating an integrated circuit, including the fabrication of an interconnect using a damascene process, the method comprising:
forming a pre-metal dielectric layer over a semiconductor device formed on a substrate;
forming a contact for electrical connection to the device through the pre-metal dielectric layer;
forming an etch stop layer over the pre-metal dielectric layer and the contact;
forming an inter-layer dielectric layer over the etch stop layer;
forming and patterning a hardmask over the inter-level dielectric layer;
forming an interconnect opening in the inter-level dielectric layer by etching through the patterned hardmask;
forming a metal layer over the inter-level dielectric layer and filling the interconnect opening;
performing a planarization process to remove at least a portion of the metal layer from over the inter-level dielectric layer;
pre-charging a reaction chamber of a plasma deposition tool without the substrate in the chamber, by generating a first reactive species from a first source gas in the presence of a first plasma at a first temperature; the first source gas including NH3 and the first temperature being higher than 400° C.;
following planarization, introducing the substrate into the pre-charged chamber, with the first plasma terminated and the first reactive species still present in the chamber;
with the substrate introduced into the pre-charged chamber, treating the substrate with a second reactive species from a second source gas in the presence of a second plasma at a second temperature; the second source gas including NH3 and He, the second temperature being lower than 400° C., and the second reactive species being started while the first reactive species is still present in the chamber; and
with the substrate still in the chamber, depositing a layer of silicon carbon nitride over a remaining portion of the metal layer using a third source gas including silicon and carbon components.

### Claim 8 (depends on 7)

The method of claim 7, further comprising removing the substrate from the chamber following depositing the layer of silicon carbon nitride; and cleaning the chamber to remove deposits from interior surfaces of the chamber; and, following the cleaning, seasoning the chamber by depositing silicon carbon nitride on the interior surfaces.

### Claim 9 (depends on 8)

The method of claim 8, wherein the time between terminating the first plasma and introducing the substrate into the pre-charged chamber is 60 seconds or less.

### Claim 10 (depends on 9)

The method of claim 9, wherein the gas having silicon and carbon components comprises trimethylsilane.