# US 7,745,327 B2 · Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime

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- Number: US 7,745,327 B2
- Document ID: US7745327B2
- Status: Granted
- Kind: B2
- Application number: 11/761,444
- Filed: 2007-06-12
- Published: 2008-07-31
- Granted: 2010-06-29
- Earliest claimed: 2007-01-31
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Axel Preusse; Michael Friedemann; Robert Seidel; Berit Freudenberg
- Web page: https://patentgrep.com/patent/US7745327B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/084: {for dual-damascene structures}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.

## Claims

### Claim 1

A method, comprising:
forming a dielectric stack layer above a metal-containing region of a semiconductor device, said metal-containing region comprising a conductive cap layer forming at least one interface with said dielectric layer stack;
forming an opening in said dielectric stack layer;
forming a first barrier layer on sidewalls of said opening;
performing a first sputter process to remove material from a bottom of said opening to form a recess in said conductive cap layer, controlling said first sputter process to reduce a thickness of said conductive cap layer at said bottom of said opening and control a depth of said recess wherein said recess does not extend through said conductive cap layer; and
filling said opening with a metal-containing material.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first barrier layer is formed by a physical vapor deposition process.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a second barrier layer on said first barrier layer and performing a second sputter process to remove material from said bottom of said opening, controlling said second sputter process to further reduce said thickness of said conductive cap at said bottom of said opening and further extend said depth of said recess wherein said recess does not extend through said conductive cap layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein said conductive cap layer comprises at least one of a compound comprised of cobalt, tungsten and phosphorous (CoWP), a compound comprised of cobalt, tungsten and boron (CoWB), a compound comprised of nickel, molybdenum and boron (NiMoB) and a compound comprised of nickel, molybdenum and phosphorous (NiMoP).

### Claim 5 (depends on 1)

The method of claim 1, wherein said metal is copper.

### Claim 6 (depends on 1)

The method of claim 1, wherein said metal-containing region represents a metal line in a metallization layer of said semiconductor device.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a trench in said dielectric layer stack, said opening extending from said trench to said conductive cap layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein forming said opening comprises providing an etch stop layer in said dielectric layer stack, performing a first etch process for etching through a first dielectric material of said dielectric layer stack and controlling said first etch process on the basis of said etch stop layer and etching said etch stop layer in a second etch process, wherein said second etch process removes more than approximately 70% of an initial thickness of said etch stop layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein said second etch process is performed on the basis of an oxygen plasma and fluorine.

### Claim 10 (depends on 7)

The method of claim 7, wherein said trench is formed after forming said opening.

### Claim 11 (depends on 7)

The method of claim 7, wherein said trench is formed prior to forming said opening.

### Claim 12

A method, comprising:
forming a dielectric layer stack above a metal-containing region of a semiconductor device, said metal-containing region comprising a conductive cap layer forming at least one interface with said dielectric layer stack;
forming an opening in said dielectric stack layer;
performing a sequence of deposition processes to form a plurality of barrier layers successively on sidewalls of said opening;
performing a respective sputter process after at least some of said deposition processes in said sequence to remove material from a bottom of said opening to form a recess in said conductive cap layer, controlling said respective sputter process to reduce a thickness of said conductive cap layer at said bottom of said opening and control a depth of said recess wherein said recess does not extend through said conductive cap layer; and
filling said opening with a metal-containing material.

### Claim 13 (depends on 12)

The method of claim 12, wherein each of said deposition processes is followed by a sputter process.

### Claim 14 (depends on 12)

The method of claim 12, wherein at least one of the deposition processes in said sequence comprises a sputter deposition process.

### Claim 15 (depends on 12)

The method of claim 12, wherein said dielectric layer comprises an etch stop layer for controlling an etch process to etch through a dielectric material formed above said etch stop layer and wherein approximately 70% or more of said etch stop layer within said opening are removed on the basis of an oxygen plasma.

### Claim 16 (depends on 12)

The method of claim 12, wherein said conductive cap layer comprises at least one of a compound comprised of cobalt, tungsten and phosphorous (CoWP), a compound comprised of cobalt, tungsten and boron (CoWB), a compound comprised of nickel, molybdenum and boron (NiMoB) and a compound comprised of nickel, molybdenum and phosphorous (NiMoP).

### Claim 17

A method, comprising:
forming a conductive cap layer above a copper-containing metal region provided in a dielectric material of a semiconductor device;
forming a dielectric layer stack above said conductive cap layer;
forming an opening in said dielectric layer stack;
forming at least a first conductive barrier layer and a second conductive barrier layer by a first deposition process and a second deposition process;
performing a first sputter process after said first deposition process and a second sputter process after said second deposition process to remove material from a bottom of said opening and form a recess in said conductive cap layer; and
controlling said first and second deposition processes and said first and second sputter processes to adjust a depth of said recess in said conductive cap layer on the basis of a target depth such that said recess does not extend through said conductive cap layer after performing said first and second deposition processes and said first and second sputter processes.

### Claim 18 (depends on 17)

The method of claim 17, wherein said target depth is selected to maintain a portion of said conductive cap layer.