# US 7,745,319 B2 · System and method for fabricating a fin field effect transistor

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- Number: US 7,745,319 B2
- Document ID: US7745319B2
- Status: Granted
- Kind: B2
- Application number: 11/508,047
- Filed: 2006-08-22
- Published: 2008-02-28
- Granted: 2010-06-29
- Earliest claimed: 2006-08-22
- Assignees: Micron Technology, Inc.
- Inventors: Sanh D. Tang; Gordon Haller
- Web page: https://patentgrep.com/patent/US7745319B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/834: {comprising FinFETs}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.

## Claims

### Claim 1

A method comprising:
depositing a layer of nitride on a substrate;
disposing a photolithographic mask on the layer of nitride, to define a location of a wall;
etching the layer of nitride to create the wall;
removing the photolithographic mask;
depositing a spacer layer adjacent to the wall;
etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate;
etching a second portion of the substrate not covered by the spacer to create a trench;
filing the trench with a dielectric material;
etching the layer of nitride to expose a part of the first portion of the substrate; and
etching the exposed part of the first portion of the substrate to a depth to create a channel.

### Claim 2 (depends on 1)

The method, as set forth in claim 1, wherein depositing the spacer layer comprises depositing a layer of Tetraethyl Orthosilicate.

### Claim 3 (depends on 1)

The method, as set forth in claim 1, wherein filing the trench comprises filing the trench with a spin-on dielectric.

### Claim 4 (depends on 1)

The method, as set forth in claim 1, comprising etching the dielectric material to approximately the same depth as the substrate.

### Claim 5 (depends on 4)

The method, as set forth in claim 4, wherein etching the dielectric material to approximately the same depth as the substrate comprises creating a fin.

### Claim 6 (depends on 5)

The method, as set forth in claim 5, wherein creating the fin comprises creating a fin that is recessed below an upper surface of the substrate.

### Claim 7 (depends on 4)

The method, as set forth in claim 4, wherein etching the dielectric material to approximately the same depth as the substrate comprises creating a first fin and a second fin.

### Claim 8 (depends on 4)

The method, as set forth in claim 4, wherein etching the exposed part of the first portion of the substrate comprises creating a first wall of the first fin and a first wall of the second fin.

### Claim 9 (depends on 4)

The method, as set forth in claim 4, comprising forming a gate deposited on the substrate.

### Claim 10 (depends on 4)

The method, as set forth in claim 4, comprising forming a gate onto a fin.

### Claim 11

A method of fabricating a transistor comprising a fin and a gate, the method comprising: performing a first etch to create a first wall of the fin in a portion of a substrate, without using a photolithographic mask in the portion; performing a second etch to create a second wall of the fin; and depositing a gate on the fin, wherein the gate is deposited after the second etch.

### Claim 12 (depends on 11)

The method, as set forth in claim 11, wherein performing the first etch comprises creating the first wall of the fin that is recessed below the upper surface of a substrate.

### Claim 13 (depends on 11)

The method, as set forth in claim 11, wherein the method comprises fabricating a transistor comprising a single gate.

### Claim 14 (depends on 11)

The method, as set forth in claim 11, wherein performing the first etch creates a first wall of another fin.

### Claim 15 (depends on 11)

The method of claim 11, wherein performing a first etch to create a first wall of the fin comprises etching an exposed part of a substrate to a depth to create a channel in the substrate.