# US 7,745,316 B2 · Method for fabricating Schottky barrier tunnel transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,745,316 B2
- Document ID: US7745316B2
- Status: Granted
- Kind: B2
- Application number: 11/930,902
- Filed: 2007-10-31
- Published: 2008-06-05
- Granted: 2010-06-29
- Earliest claimed: 2006-12-01
- Assignees: Electronics and Telecommunications Research Institute
- Inventors: Yark-Yeon Kim; Seong-Jae Lee; Moon-Gyu Jang; Tae-Youb Kim; Chel-Jong Choi; Myung-Sim Jun; Byoung-Chul Park
- Web page: https://patentgrep.com/patent/US7745316B2

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

## Claims

### Claim 1

A method for fabricating a Schottky barrier tunnel transistor, comprising:
a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate;
b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern;
c) removing the sacrificial pattern to expose the top surface of the silicon pattern;
d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern; and
e) forming spacers on both sidewalls of the gate electrode after forming the gate electrode.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step b) includes the steps of:
b1) forming a photoresist pattern having an opening at a region corresponding to a region where the source/drain region is to be formed; and
b2) forming the metal layer to fill the opening of the photoresist pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metal layer is formed from among the group of transition metals and rare earth metals.

### Claim 4 (depends on 1)

The method of claim 1, further comprising the step of f) forming a passivation layer on the source/drain region after forming the source/drain region.

### Claim 5 (depends on 4)

The method of claim 4, wherein the passivation layer is formed of tantalum (Ta).

### Claim 6 (depends on 1)

The method of claim 1, wherein the sacrificial pattern is formed of tungsten (W).

### Claim 7 (depends on 6)

The method of claim 6, wherein the sacrificial pattern is removed using hydrogen peroxide.

### Claim 8 (depends on 7)

The method of claim 7, wherein the hydrogen peroxide is heated to a temperature ranging from approximately 50° C. to approximately 200° C.

### Claim 9 (depends on 1)

The method of claim 1, further comprising the step of g) forming a glue layer on the buried oxide layer before forming the source/drain region.

### Claim 10 (depends on 9)

The method of claim 9, wherein the glue layer is formed of chromium (Cr) or tantalum (Ta).

### Claim 11 (depends on 1)

The method of claim 1, further comprising, after forming the source/drain region, the step of h) performing a thermal treatment to react the metal layer of the source/drain region with silicon of the silicon pattern, thereby forming a metal silicide layer along a boundary between the source/drain region and the silicon pattern.

### Claim 12 (depends on 1)

The method of claim 1, further comprising, after removing the sacrificial pattern to expose the top surface of the silicon pattern, the step of i) performing a thermal treatment to react the metal layer of the source/drain region with silicon of the silicon pattern, thereby forming a metal silicide layer along a boundary between the source/drain region and the silicon pattern.

### Claim 13 (depends on 1)

The method of claim 1, further comprising, after forming the gate electrode, the step of j) performing a thermal treatment to react the metal layer of the source/drain region with silicon of the silicon pattern, thereby forming a metal silicide layer along a boundary between the source/drain region and the silicon pattern.

### Claim 14

A method for fabricating a Schottky barrier tunnel transistor, comprising:
a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate;
b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, including the steps of
b1) forming a photoresist pattern having an opening at a region corresponding to a region where the source/drain region is to be formed, and
b2) forming the metal layer to fill the opening of the photoresist pattern,
the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern;
c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and
d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

### Claim 15

A method for fabricating a Schottky barrier tunnel transistor, comprising:
a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate;
b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern;
c) removing the sacrificial pattern to expose the top surface of the silicon pattern;
d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern; and
j) performing a thermal treatment to react the metal layer of the source/drain region with silicon of the silicon pattern after forming the gate electrode, thereby forming a metal silicide layer along a boundary between the source/drain region and the silicon pattern.