# US 7,745,313 B2 · Substrate release methods and apparatuses

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- Number: US 7,745,313 B2
- Document ID: US7745313B2
- Status: Granted
- Kind: B2
- Application number: 12/473,811
- Filed: 2009-05-28
- Published: 2010-01-28
- Granted: 2010-06-29
- Earliest claimed: 2008-05-28
- Assignees: Solexel, Inc.
- Inventors: David Xuan-Qi Wang; Mehrdad M. Moslehi
- Web page: https://patentgrep.com/patent/US7745313B2

## CPC

- H10F 71/00: Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00)
- H10F 71/1395: {for thin-film devices}
- H10P 90/1924: {with separation/delamination along a porous layer}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step.

## Claims

### Claim 1

A method of forming a 3-D thin film semiconductor substrate (TFSS) by releasing it from a semiconductor template through the use of a buried porous semiconductor layer, comprising the steps of:
forming a buried porous semiconductor layer on a template, said buried porous semiconductor layer formed conformal to said template;
forming a TFSS on said buried porous semiconductor layer, said TFSS, said buried porous semiconductor layer, and said template forming a wafer, said TFSS having 3-D features in contact with said porous semiconductor layer;
performing at least one release step which fractures at least a portion of said buried porous semiconductor layer; and
separating said TFSS and said template.

### Claim 2 (depends on 1)

The method of claim 1, wherein said release step further comprises repeating said release step for a plurality of cycles.

### Claim 3 (depends on 1)

The method of claim 1, wherein said release step further comprises the step of applying a hydrostatic pressure to said wafer.

### Claim 4 (depends on 3)

The method of claim 3, wherein said hydrostatic pressure is in the range of approximately 0.1 GPa to 100 GPa.

### Claim 5 (depends on 1)

The method of claim 1, wherein said release step further comprises thermally expanding and/or contracting said buried porous semiconductor layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein said step of thermally expanding and/or contracting said buried porous semiconductor layer further comprises the step of contacting at least one temperature controlled chuck to said wafer.

### Claim 7 (depends on 6)

The method of claim 6, wherein said at least one temperature controlled wafer chuck is in a temperature range bound between approximately −50° and 350° C.

### Claim 8 (depends on 5)

The method of claim 5, wherein said step of thermally expanding or contracting said buried porous semiconductor layer further comprises the step of heating said wafer through infrared (IR) laser irradiation.

### Claim 9 (depends on 8)

The method of claim 8, wherein said step of heating said wafer using IR laser irradiation further comprises the step of heating said wafer using a C02 laser.

### Claim 10 (depends on 8)

The method of claim 8, wherein said step of heating said wafer using IR laser irradiation source further comprises the step of heating said wafer using a YAG laser.

### Claim 11 (depends on 5)

The method of claim 5, wherein said step of thermally expanding or contracting said buried porous semiconductor layer further comprises the step of dispensing or immersing a wafer in a heating or cooling source.

### Claim 12 (depends on 11)

The method of claim 11, wherein said cooling source comprises at least one of liquid nitrogen, inert gases, cold air, or CO2 snow (dry ice) or said heating source comprises at lease one of hot liquid, DI water, steam, temperature controlled oven, or hot air.

### Claim 13 (depends on 5)

The method of claim 5, wherein said step of thermally expanding or contracting said buried porous semiconductor layer further comprises the step of heating said wafer with a Rapid Thermal Processing (RTP) heating source.

### Claim 14 (depends on 1)

The method of claim 1, wherein said release step further comprises the step of exposing said wafer to ultrasonic energy.

### Claim 15 (depends on 1)

The method of claim 1, wherein said release step further comprises the step of mechanically bending said wafer.

### Claim 16 (depends on 1)

The method of claim 1, wherein said release step further comprises the step of introducing a liquid or gas into the pores of said buried porous semiconductor layer and then expanding and/or contracting said liquid or said gas.

### Claim 17 (depends on 16)

The method of claim 16, wherein said liquid or said gas comprises an etchant.

### Claim 18 (depends on 16)

The method of claim 16, wherein said step of expansion and/or contraction further comprises the step of heating or cooling of said liquid or gas, said heating or cooling resulting in a phase change of said liquid or gas.

### Claim 19 (depends on 16)

The method of claim 16, wherein said expansion step further comprises the step of loading said wafer into a vacuum chamber and rapidly depressurizing said vacuum chamber.

### Claim 20 (depends on 1)

The method of claim 1, wherein a said release step further comprises a final cleaning step wherein said final cleaning step further comprises a megasonic or ultrasonic cleaning step or a mechanical precision pulling step.

### Claim 21 (depends on 1)

The method of claim 1, wherein said step of forming a buried porous semiconductor layer on a template further comprises the step of forming a buried porous silicon layer.

### Claim 22 (depends on 1)

The method of claim 1, wherein said step of forming a buried porous semiconductor layer on a template further comprises the step of forming said buried porous semiconductor layer on a silicon template.

### Claim 23 (depends on 1)

The method of claim 1, wherein forming a TFSS on said buried porous semiconductor layer further comprises the step of forming a thin-film silicon substrate.