# US 7,745,290 B2 · Methods of fabricating semiconductor device including fin-fet

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- Number: US 7,745,290 B2
- Document ID: US7745290B2
- Status: Granted
- Kind: B2
- Application number: 11/773,372
- Filed: 2007-07-03
- Published: 2008-05-29
- Granted: 2010-06-29
- Earliest claimed: 2006-07-03
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jun Seo; Jong-Heui Song; Jae-Seung Hwang; Min-Chul Chae; Woo-Jin Cho; Yun-Seung Kang; Young-Mi Lee
- Web page: https://patentgrep.com/patent/US7745290B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming sacrificial bars on a semiconductor substrate;
patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate;
forming a device isolation layer to fill a space between the sacrificial islands;
selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands; and
anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region;
wherein before forming the sacrificial islands:
forming a mask layer to fill a space between the sacrificial bars; and
planarizing the mask layer to expose top surfaces of the sacrificial bars,
wherein the mask layer comprises a material having an etch selectivity with respect to the sacrificial bars; and
wherein forming the sacrificial islands comprises:
patterning the mask layer and the sacrificial bars in a direction substantially perpendicular to a major axis of the sacrificial bars to form the sacrificial islands and mask patterns disposed therebetween; and
etching the exposed surfaces of the sacrificial islands using the mask patterns as etch masks to partially expose the top surface of the semiconductor substrate between the mask patterns.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein forming the sacrificial islands comprises:
patterning the sacrificial bars in a direction substantially perpendicular to a major axis of the sacrificial bars.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein etching the exposed surfaces of the sacrificial islands comprises using an etchant including phosphoric acid.

### Claim 4 (depends on 1)

The method as recited in claim 1, further comprising before etching the exposed surfaces of the sacrificial islands:
etching the semiconductor substrate using the sacrificial islands and the mask patterns as etch masks to form trenches, the trenches defining active patterns.

### Claim 5 (depends on 4)

The method as recited in claim 4, wherein forming the device isolation layer comprises:
forming an insulation layer filling the trenches; and
planarizing the insulation layer to form the device isolation layer, the device isolation layer exposing the top surfaces of the mask patterns and the sacrificial islands.

### Claim 6 (depends on 4)

The method as recited in claim 4, further comprising, after forming the recessed channel region:
etching the device isolation layer and the mask patterns to expose the top surface and upper sidewalls of the active patterns;
forming a gate insulating layer to cover the exposed surfaces of the active patterns; and
forming a gate electrode on the gate insulating layer filling the recessed channel region, the gate electrode crossing over the active patterns.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein the sacrificial bars comprise silicon nitride or silicon oxynitride, and the mask layer and the device isolation layer comprise silicon oxide.

### Claim 8 (depends on 7)

The method as recited in claim 7, wherein selectively removing the sacrificial islands comprises using an etchant including phosphoric acid.

### Claim 9

A method of fabricating a semiconductor device, the method comprising:
forming sacrificial bars on a semiconductor substrate;
forming a mask layer to fill a space between the sacrificial bars;
patterning the mask layer and the sacrificial bars in a direction substantially perpendicular to a major axis of the sacrificial bars to form mask patterns and sacrificial islands disposed therebetween;
etching the semiconductor substrate using the mask patterns and the sacrificial islands as etch masks to form trenches, the trenches defining an active pattern;
etching the sacrificial islands to partially expose a top surface of the active pattern between the mask patterns;
forming a device isolation layer to fill the trenches and surround the mask patterns and the sacrificial islands;
selectively removing the sacrificial islands to expose the active pattern;
anisotropically etching the exposed active pattern using the device isolation layer and the mask patterns as etch masks to form a recessed channel region;
etching the device isolation layer to expose a top surface and an upper sidewall of the active pattern; and
forming a gate electrode to fill the recessed channel region, the gate electrode crossing over the active pattern.

### Claim 10 (depends on 9)

The method as recited in claim 9, wherein etching the sacrificial islands to partially expose the top surface of the active pattern between the mask patterns comprises:
isotropically etching the exposed surface of the sacrificial islands to a predetermined depth using a wet etch recipe having an etch selectivity with respect to the mask patterns and the semiconductor substrate.

### Claim 11 (depends on 10)

The method as recited in claim 10, wherein, after etching the sacrificial islands, the sacrificial islands have a substantially rectangular solid shape.

### Claim 12 (depends on 11)

The method as recited in claim 11, wherein, after etching the sacrificial islands, edges of the sacrificial islands exposed between the mask patterns have a curvature radius of less than one-fifth of a width of the mask patterns.