# US 7,745,288 B2 · Semiconductor device and a method of manufacturing the same

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- Number: US 7,745,288 B2
- Document ID: US7745288B2
- Status: Granted
- Kind: B2
- Application number: 11/717,053
- Filed: 2007-03-13
- Published: 2007-10-04
- Granted: 2010-06-29
- Earliest claimed: 2006-04-04
- Assignees: Renesas Technology Corp.
- Inventors: Koichi Toba; Yasushi Ishii; Yoshiyuki Kawashima; Satoru Machida; Munekatsu Nakagawa; Kentaro Saito; Toshikazu Matsui; Takashi Hashimoto; Kosuke Okuyama
- Web page: https://patentgrep.com/patent/US7745288B2

## CPC

- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/685: {from the channel}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming an isolation region in a main surface of a semiconductor substrate such that an active region is defined by the isolation region;
(b) forming over the main surface of the semiconductor substrate an insulating film for charge storage of a non-volatile memory cell;
(c) forming over the insulating film for charge storage a first gate electrode having a first side face and a second side face, the first and second side faces being positioned at opposite sides of the first gate electrode in a direction along the main surface of the semiconductor substrate;
(d) forming in the main surface of the semiconductor substrate a first semiconductor region in a self-alignment manner with respect to the first side face of the first gate electrode;
(e) after the step (d), depositing a first insulating film over the main surface of the semiconductor substrate;
(f) after the step (e), etching the first insulating film and a surface of the first semiconductor region so as to form a first insulating film side wall over the first side face of the first gate electrode and a first depression in a region of the first semiconductor adjacent to the first insulating film side wall;
(g) after the step (f), forming in the main surface of the semiconductor substrate a second semiconductor region in a self-alignment manner with respect to a side face of the first insulating film side wall, the second semiconductor region being electrically coupled to the first semiconductor region;
(h) after the step (g), depositing a second insulating film over the main surface of the semiconductor surface;
(i) after the step (h), etching the second insulating film so as to form a second insulating film side wall over the side face of the first insulating film side wall and to cover a side surface of the semiconductor substrate exposed by the first depression; and
(j) after the step (i), forming a first silicide layer over the second semiconductor region, the first silicide layer being formed in a self-alignment manner with respect to a side face of the second insulating film side wall.

### Claim 2 (depends on 1)

A method according to claim 1,
wherein step (i) includes:
forming an insulating film pattern which covers a region over the main surface of the semiconductor substrate, such that silicide is not formed over said region in step (j).

### Claim 3 (depends on 1)

A method according to claim 1,
wherein the step of forming the isolation region includes the steps of:
forming a trench in the main surface of the semiconductor substrate; and
burying an insulating film for isolation into the trench, and
wherein the step (i) includes a step of:
forming a fifth insulating film side wall in a third depression, which is formed in a portion adjacent to the active region over an upper surface of the buried insulating film for isolation, so as to cover a side face of the semiconductor substrate exposed by the third depression.

### Claim 4 (depends on 1)

A method according to claim 1, further comprising, before the step (b), the steps of:
forming a gate insulating film in a non-volatile memory cell region over the main surface of the semiconductor substrate; and
forming a second gate electrode over the gate insulating film, the second gate electrode having a third side face opposed to the second side face of the first gate electrode with the insulating film for charge storage therebetween and a fourth side face positioned opposite to the third side face in a direction along the main surface of the semiconductor substrate,
wherein step (d) includes forming a third semiconductor region over the main surface of the semiconductor substrate in a self-alignment manner with respect to the fourth side face of the second gate electrode,
wherein step (f) includes forming a third insulating film side wall over the fourth side face of the second gate electrode and etching a surface of the third semiconductor region so as to form a second depression in a region of the second semiconductor region adjacent to the third insulating film side wall,
wherein step (g) includes forming a fourth semiconductor region in the main surface of the semiconductor substrate in a self-alignment manner with respect to a side face of the third insulating film side wall, the fourth semiconductor region being electrically coupled to the third semiconductor region,
wherein step (i) includes forming a fourth insulating film side wall over the side face of the third insulating film side wall so as to cover a side surface of the semiconductor substrate exposed by the second depression, and
wherein step (j) includes forming a second silicide layer over the fourth semiconductor region in a self-alignment manner with respect to a side face of the fourth insulating film side wall.

### Claim 5 (depends on 1)

A method according to claim 1, wherein a thickness of the second insulating film side wall is in the range of 10 to 80 nm.

### Claim 6 (depends on 1)

A method according to claim 1, wherein step (b) includes:
(b1) forming over the main surface of the semiconductor substrate a fifth insulating film of silicon oxide;
(b2) after step (b1), forming over the main surface of the semiconductor substrate a sixth insulating film of silicon nitride; and
(b3) after step (b2), forming over the main surface of the semiconductor substrate a seventh insulating film of silicon oxide.