# US 7,745,285 B2 · Methods of forming and operating NAND memory with side-tunneling

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- Number: US 7,745,285 B2
- Document ID: US7745285B2
- Status: Granted
- Kind: B2
- Application number: 11/693,765
- Filed: 2007-03-30
- Published: 2008-10-02
- Granted: 2010-06-29
- Earliest claimed: 2007-03-30
- Assignees: SanDisk Corporation
- Inventors: Nima Mokhlesi
- Web page: https://patentgrep.com/patent/US7745285B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.

## Claims

### Claim 1

A method of forming a NAND flash memory array comprising: forming a first gate dielectric layer that includes a blocking layer to block electron tunneling through the first gate dielectric layer;
forming a first floating gate layer over the first gate dielectric layer; patterning the first gate dielectric layer and the first floating gate layer in the same pattern to leave first floating gate portions and openings between first floating gate portions;
forming a second gate dielectric layer within the openings, the second gate dielectric layer including a blocking layer to block electron tunneling through the second gate dielectric layer; forming a second floating gate portions over the second gate dielectric layer within the openings;
etching the first and second floating gate portions so that first and second floating gate portions have an inverted-T shape in cross section;
and forming control gates that extend between neighboring floating gate portions.

### Claim 2 (depends on 1)

The method of claim 1 wherein the blocking layer includes Silicon Nitride.

### Claim 3 (depends on 1)

The method of claim 1 further comprising forming word lines that overlie the control gates and connect control gates in the word line direction.

### Claim 4 (depends on 1)

The method of claim 1 wherein etching the first and second floating gate portions is performed using masking portions that are defined by sidewall spacers.

### Claim 5 (depends on 1)

The method of claim 1 further comprising forming a tunnel dielectric layer between the control gates and the first and second floating gate portions.