# US 7,745,284 B2 · Method of manufacturing flash memory device with conductive spacers

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- Number: US 7,745,284 B2
- Document ID: US7745284B2
- Status: Granted
- Kind: B2
- Application number: 11/500,594
- Filed: 2006-08-08
- Published: 2007-07-12
- Granted: 2010-06-29
- Earliest claimed: 2005-12-28
- Assignees: Hynix Semiconductor Inc.
- Inventors: Joo Won Hwang; Byung Soo Park; Ga Hee Lee
- Web page: https://patentgrep.com/patent/US7745284B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B 41/30: characterised by the memory core region
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/44: with a control gate layer also being used as part of the peripheral transistor
- H10B 41/47: with a floating-gate layer also being used as part of the peripheral transistor
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacturing process of highly integrated semiconductor devices. It is therefore possible to minimize interference between neighboring cells.

## Claims

### Claim 1

A method of manufacturing a flash memory device, comprising:
providing a semiconductor substrate in which a plurality of regions including a cell region and a high-voltage transistor region are defined;
etching a surface of the semiconductor substrate of the high-voltage transistor region so that a height of the cell region of the semiconductor substrate is higher than that of the high-voltage transistor region;
forming a tunnel oxide film on a non-etched semiconductor substrate of the cell region;
forming a single gate oxide film on the etched semiconductor substrate of the high-voltage transistor region;
forming a first conductive layer and a hard mask film over the tunnel oxide film and the gate oxide film;
etching the hard mask film, the first conductive layer, and the semiconductor substrate to form a trench;
filling the trench with an insulating film to form an isolation film;
etching an upper portion of the isolation film formed in the cell region and the high-voltage transistor region; and
forming a dielectric film and a second conductive layer on the first conductive layer; and
patterning the second conductive layer to form a cell gate and a high-voltage transistor gate,
wherein the tunnel oxide film and the single gate oxide film are formed by performing oxidization.

### Claim 2 (depends on 1)

The method of claim 1, comprising etching the semiconductor substrate of the high-voltage transistor region taking a thickness of the tunnel oxide film and a thickness of the single gate oxide film into consideration such that the tunnel oxide film and the single gate oxide film have the same height from the surface of the semiconductor substrate.

### Claim 3 (depends on 1)

The method of claim 1, comprising forming the first conductive layer to a thickness of 700 Å to 1500 Å by laminating an undoped polysilicon film and a doped polysilicon film.

### Claim 4 (depends on 3)

The method of claim 3, wherein the undoped polysilicon film has a thickness, which is half or less a thickness of the first conductive layer.

### Claim 5 (depends on 1)

The method of claim 1, comprising etching the isolation film of the cell region and the high-voltage transistor region by a wet etch process using buffered oxide etchant (BOE).