# US 7,745,283 B2 · Method of fabricating memory transistor

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- Number: US 7,745,283 B2
- Document ID: US7745283B2
- Status: Granted
- Kind: B2
- Application number: 11/023,719
- Filed: 2004-12-28
- Published: 2005-06-09
- Granted: 2010-06-29
- Earliest claimed: 2002-08-08
- Assignees: Micron Technology, Inc.
- Inventors: Kirk D. Prall
- Web page: https://patentgrep.com/patent/US7745283B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0277: {forming conductor-insulator-semiconductor or Schottky barrier source or drain regions}
- H10D 30/685: {from the channel}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

## Claims

### Claim 1

A method of forming a memory transistor, comprising:
providing a substrate comprising semiconductive material;
forming laterally spaced-apart source/drain structures within the semiconductive material, at least one of the source/drain structures comprising a Schottky contact to the semiconductive material, wherein the Schottky contact comprises one or more members of the group consisting of Cu, Pb and Hf;
forming a charge storage gate laterally between the spaced-apart source/drain structures, the charge storage gate having a first oxide layer, a second oxide layer, and a nitride layer sandwiched between the first and second oxide layers, wherein charge carriers injected into the charge storage gate are trapped in the nitride layer which enables the memory transistor to be programmed to a plurality of distinct charge storage states; and
forming a control gate disposed operatively elevationally over the charge storage gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a charge storage gate comprises:
forming a SONOS structure; and
forming the control gate atop the SONOS structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming a charge storage gate comprises:
forming a SONOS structure; and
forming the control gate to comprise polysilicon disposed atop the SONOS structure.

### Claim 4 (depends on 1)

The method of claim 1, wherein the Schottky contact is to p-type material.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming spaced-apart source/drain structures comprises forming Schottky contacts to p-type material.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming spaced-apart source/drain structures comprises forming Schottky contacts.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming spaced-apart source/drain structures comprises forming Schottky contacts to n-type semiconductor material.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming spaced-apart source/drain structures comprises forming at least one Schottky contact to n-type semiconductor material.

### Claim 9

A memory transistor structure comprising:
a substrate comprising semiconductive material and having an upper surface;
laterally spaced-apart source/drain structures, at least one of the source/drain structures comprising a Schottky contact to the semiconductive material, wherein the Schottky contact comprises one or more members of the group consisting of Cu, Pb and Hf;
a charge storage gate disposed laterally between the spaced-apart source/drain structures, the charge storage gate having a first oxide layer, a second oxide layer, and an intermediate layer sandwiched between the first and second oxide layers, wherein the charge storage gate is configured to trap charge carriers, injected into the charge storage gate, in the intermediate layer to program the memory transistor structure to any of a plurality of distinct charge storage states; and
a control gate disposed operatively elevationally over the charge storage gate.

### Claim 10 (depends on 9)

The memory transistor structure of claim 9, wherein the charge storage gate comprises:
a SONOS structure defining a first oxide layer, a second oxide layer, and a nitride layer; and
wherein the control gate is atop the SONOS structure.

### Claim 11 (depends on 9)

The memory transistor structure of claim 9, wherein the charge storage gate comprises:
a SONOS structure defining a first oxide layer, a second oxide layer, and a nitride layer; and
wherein the control gate comprises polysilicon disposed atop the SONOS structure.

### Claim 12 (depends on 9)

The memory transistor structure of claim 9, wherein the Schottky contact is to p-type material.

### Claim 13 (depends on 9)

The memory transistor structure of claim 9, wherein the spaced-apart source/drain structures comprise Schottky contacts to p-type material.

### Claim 14 (depends on 9)

The memory transistor structure of claim 9, wherein the spaced-apart source/drain structures comprise Schottky contacts.

### Claim 15 (depends on 9)

The memory transistor structure of claim 9, wherein the spaced-apart source/drain structures comprise Schottky contacts to n-type semiconductor material.

### Claim 16 (depends on 9)

The memory transistor structure of claim 9, wherein the spaced-apart source/drain structures comprise at least one Schottky contact to n-type semiconductor material.

### Claim 17

A method of forming a memory transistor, comprising:
providing a substrate comprising semiconductive material;
forming laterally spaced-apart source/drain structures within the semiconductive material, at least one of the source/drain structures comprising a Schottky contact to the semiconductive material, wherein the Schottky contact comprises one or more members of the group consisting of Cu, Pb and Hf;
forming a charge storage gate laterally between the spaced-apart source/drain structures by forming a SONOS structure; and
forming a control gate disposed operatively elevationally over the SONOS structure.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming a charge storage gate comprises disposing polysilicon atop the SONOS structure.

### Claim 19

A memory transistor, comprising:
a semiconductive material;
spaced-apart source/drain structures, at least one of the source/drain structures comprising a Schottky contact to the semiconductive material, wherein the Schottky contact comprises one or more members of the group consisting of Cu, Pb and Hf;
a charge storage structure between the spaced-apart source/drain structures; and
a control gate disposed operatively over the charge storage structure.

### Claim 20 (depends on 19)

The memory transistor of claim 19, wherein the charge storage structure comprises a first oxide material, a second oxide material, and a charge storage material between the first and second oxide materials, wherein the charge storage structure is configured to trap charge carriers injected into the charge storage structure.