# US 7,745,280 B2 · Metal-insulator-metal capacitor structure

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- Number: US 7,745,280 B2
- Document ID: US7745280B2
- Status: Granted
- Kind: B2
- Application number: 12/129,672
- Filed: 2008-05-29
- Published: 2009-12-03
- Granted: 2010-06-29
- Earliest claimed: 2008-05-29
- Assignees: United Microelectronics Corp.
- Inventors: Yu-Ho Chiang
- Web page: https://patentgrep.com/patent/US7745280B2

## CPC

- H01G 4/008: Selection of materials
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)

## Abstract

A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.

## Claims

### Claim 1

A metal-insulator-metal (MIM) capacitor structure, comprising:
a substrate;
a first metal layer and a conductor layer disposed in said substrate;
a patterned buffer layer covering said first metal layer and said conductor layer and having a first opening to expose said first metal layer;
a second metal layer disposed in said first opening, and said second metal layer and said first metal layer together forming a lower electrode plate;
a barrier layer disposed on said second metal layer and covering part of said patterned buffer layer, wherein the area barrier layer is larger than that of said second metal layer;
a dielectric layer disposed on said barrier layer;
an upper electrode plate disposed on said dielectric layer; and
a passivation layer covering said upper electrode plate and said patterned buffer layer.

### Claim 2 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said conductive layer, said first metal layer and said second metal layer comprise copper.

### Claim 3 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said patterned buffer layer comprises a nitride.

### Claim 4 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said conductive layer is electrically connected to said first metal layer.

### Claim 5 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said barrier layer is selected from a group consisting of TaN, Ta, TiN and a combination thereof.

### Claim 6 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said barrier layer and said upper electrode plate are of the same area size.

### Claim 7 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said dielectric layer is selected from a group consisting of silicon oxide, silicon nitride, a high K material and a combination thereof.

### Claim 8 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said upper electrode plate is selected from a group consisting of Al, Ti, TiN and a combination thereof.

### Claim 9 (depends on 1)

The metal-insulator-metal (MIM) capacitor structure of claim 1, wherein said passivation layer comprises a nitride.

### Claim 10

A method for manufacturing a metal-insulator-metal (MIM) capacitor structure, comprising:
providing a substrate comprising a first metal and a conductive layer;
forming a patterned buffer layer covering said first metal and said conductive layer, wherein said patterned buffer layer has a first opening to expose said first metal;
filling said first opening with a second metal so that said second metal and said first metal together form a lower electrode plate;
forming a barrier layer to cover said second metal and said patterned buffer layer;
forming a dielectric layer to cover said barrier layer;
forming an upper electrode plate layer to cover said dielectric layer;
selectively removing said upper electrode plate layer, said dielectric layer and said barrier layer by a lithographic and etching procedure to expose said patterned buffer layer and form an upper electrode plate, wherein said barrier layer covers part of said patterned buffer layer; and
forming a passivation layer to cover said upper electrode plate, said dielectric layer, said barrier layer and said patterned buffer layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
selectively removing said passivation layer and said patterned buffer layer to expose part of said upper electrode plate and part of said conductive layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein said first metal is electrically connected to said conductive layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein said buffer layer comprises a nitride.

### Claim 14 (depends on 10)

The method of claim 10, wherein said conductive layer, said first metal and said second metal comprise copper and said barrier layer is selected from a group consisting of TaN, Ta, TiN and a combination thereof.

### Claim 15 (depends on 10)

The method of claim 10, wherein said dielectric layer is selected from a group consisting of silicon oxide, silicon nitride, a high K material and a combination thereof.

### Claim 16 (depends on 10)

The method of claim 10, wherein said upper electrode plate is selected from a group consisting of Al, Ti, TiN and a combination thereof.

### Claim 17 (depends on 10)

The method of claim 10, wherein said passivation layer comprises a nitride.