# US 7,745,278 B2 · Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

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- Number: US 7,745,278 B2
- Document ID: US7745278B2
- Status: Granted
- Kind: B2
- Application number: 12/211,530
- Filed: 2008-09-16
- Published: 2009-01-08
- Granted: 2010-06-29
- Earliest claimed: 2004-06-04
- Assignees: International Business Machines Corporation
- Inventors: Nestor A. Bojarczuk, Jr.; Cyril Cabral, Jr.; Eduard A. Cartier; Matthew W. Copel; Martin M. Frank; Evgeni P. Gousev; Supratik Guha; Rajarao Jammy; Vijay Narayanan; Vamsi K. Paruchuri
- Web page: https://patentgrep.com/patent/US7745278B2

## CPC

- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

## Claims

### Claim 1

A method of forming a complementary metal oxide semiconductor (CMOS) structure having improved threshold voltage and flatband voltage stability comprising:
providing a semiconductor substrate having a first device region and a second device region;
forming a dielectric stack atop said semiconductor substrate including said first device region and said second device region, said dielectric stack comprising an insulating interlayer atop a high k dielectric, the high k dielectric present on the semiconductor substrate;
removing said insulating interlayer from said first device region, without removing said insulating interlayer from said second device region;
forming a gate conductor atop said insulating interlayer in said second device region and said high k dielectric in said first device region, wherein the first device region is an area for at least one nFET device and said second device region is an area for at least one pFET device, wherein said insulating interlayer stabilizes said second device regions threshold voltage and flatband voltage without shifting said first device region's threshold voltage and flatband voltage; and
etching said gate conductor, said insulating interlayer and said high k dielectric to provide at least one gate stack in said second device region and at least one gate stack in said first device region, wherein the at least one gate stack in the first device region comprises, from bottom to top, the high k gate dielectric disposed directly on said semiconductor substrate and the gate conductor disposed on the high k gate dielectric, and the at least one gate stack in the second device region comprises, from bottom to top, the high k gate dielectric disposed directly on said semiconductor substrate, an insulating interlayer atop said high k gate dielectric, and the gate conductor atop said insulating interlayer.

### Claim 2 (depends on 1)

The method of claim 1 wherein said insulating interlayer comprises an insulating metal nitride.

### Claim 3 (depends on 2)

The method of claim 2 wherein said insulating metal nitride further comprises oxygen.

### Claim 4 (depends on 1)

The method of claim 1 wherein said insulating interlayer comprises aluminum nitride (AlN), aluminum oxynitride (AlOxNy), boron nitride (BN), boron oxynitride (BOxNy), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN), indium oxynitride (InON) or combinations thereof.

### Claim 5 (depends on 1)

The method of claim 1 wherein said insulating interlayer comprises AlN or AlOxNy.

### Claim 6 (depends on 1)

The method of claim 1 wherein said high k dielectric comprises HfO2, hafnium silicate or hafnium silicon oxynitride.

### Claim 7 (depends on 1)

The method of claim 1 wherein said insulating interlayer is formed by deposition or thermal growing.

### Claim 8 (depends on 7)

The method of claim 7 wherein said deposition comprises plating, sputtering, atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD).

### Claim 9 (depends on 1)

The method of claim 1 wherein said high k dielectric is formed by deposition or thermal growing.

### Claim 10 (depends on 9)

The method of claim 9 wherein said deposition comprises chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal organic chemical vapor deposition (MOCVD), high-density chemical vapor deposition (HDCVD), plating, sputtering, evaporation or chemical solution deposition.

### Claim 11 (depends on 9)

The method of claim 9 wherein said thermal growing comprises oxidation, nitridation, or oxynitridation.

### Claim 12 (depends on 1)

The method of claim 1 wherein said gate conductor comprises Si, Ge, SiGe, SiGeC, W, Ir, Re, Ru, Ti, Ta, Hf, Mo, Nb, Ni, Al, metal silicides, metallic nitrides, or a combination thereof.

### Claim 13 (depends on 1)

The method of claim 1 wherein removing said insulating interlayer from said first device region without removing said insulating interlayer from said second device region further comprises
forming a block mask atop said second device region, wherein said first device region is exposed; and
etching said insulating interlayer from said first device region, said etching comprising an etch chemistry that removes said insulating interlayer without substantially etching said block mask and said high k dielectric in said first device region.

### Claim 14 (depends on 13)

The method of claim 13 wherein said block mask comprises a patterned photoresist layer.

### Claim 15 (depends on 14)

The method of claim 14 wherein forming said block mask comprises
blanket depositing a photoresist layer atop said semiconductor substrate;
exposing said photoresist layer to a pattern of radiation; and
developing said pattern into said photoresist layer to provide said block mask overlying said second device region.

### Claim 16 (depends on 13)

The method of claim 13 wherein said block mask comprises a dielectric selected from the group consisting of silicon oxides, silicon carbides, silicon nitrides, silicon carbonitrides, silsequioxanes, siloxanes, and boron phosphate silicate glass (BPSG).

### Claim 17 (depends on 13)

The method of claim 13 wherein said etch chemistry is a wet etch comprising HCl and an oxidizing agent.

### Claim 18 (depends on 17)

The method of claim 17 wherein said etch chemistry has a pH ranging from about 1 to about 7.

### Claim 19 (depends on 18)

The method of claim 18 wherein said etch chemistry has a pH ranging from about 2 to about 6.

### Claim 20 (depends on 17)

The method of claim 17 wherein said etch chemistry comprises a 3:1 HCl/H2O2 peroxide solution.

### Claim 21 (depends on 13)

The method of claim 13 wherein said insulating interlayer comprises aluminum nitride (AlN), aluminum oxynitride (AlOxN), boron nitride (BN), boron oxynitride (BOxNy), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN), indium oxynitride (InON) or combinations thereof.

### Claim 22 (depends on 13)

The method of claim 13 wherein said insulating interlayer comprises AlN.