# US 7,745,275 B2 · Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,745,275 B2 - Document ID: US7745275B2 - Status: Granted - Kind: B2 - Application number: 12/232,107 - Filed: 2008-09-10 - Published: 2010-03-11 - Granted: 2010-06-29 - Earliest claimed: 2008-09-10 - Assignees: Arm Limited - Inventors: Gregory Munson Yeric; Marlin Wayne Frederick - Web page: https://patentgrep.com/patent/US7745275B2 ## CPC - H10W 20/0698: {Local interconnections} - H10D 89/10: Integrated device layouts - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region. ## Claims ### Claim 1 A method of making an integrated circuit, said method comprising the steps of: forming on a diffusion region of a semiconductor substrate a gate electrode spaced by a gate insulator layer from said diffusion region and at least one local interconnect conductor, each local interconnect conductor respectively forming one of a source electrode and a drain electrode and said at least one local interconnect conductor extending above the diffusion region a distance comparable to a distance said gate electrode extends above the diffusion region; depositing an upper insulator layer over said diffusion region, said gate electrode and said at least one local interconnect conductor; etching through said upper insulator layer (a) at least one electrode opening, said opening reaching an upper surface of said at least one local interconnect conductor and (b) a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, etching of said gate opening being such that said gate opening has a maximum depth insufficient to reach said diffusion region; and depositing an electrode connection conductor in each of said openings. ### Claim 2 (depends on 1) A method as claimed in claim 1, wherein said at least one local interconnect conductor comprises a drain local interconnect conductor and a source local interconnect conductor, a drain opening reaching to an upper surface of said drain local interconnect conductor and a source opening reaching to an upper surface of said source local interconnect conductor. ### Claim 3 (depends on 2) A method as claimed in claim 2, wherein said gate electrode is disposed on said diffusion region between said source local interconnect conductor and said drain local interconnect conductor. ### Claim 4 (depends on 1) A method as claimed in claim 1, wherein said one or more electrode openings overlie said diffusion region. ### Claim 5 (depends on 1) A method as claimed in claim 1, wherein said at least one local interconnect conductor and said gate electrode are substantially parallel rectilinear bodies. ### Claim 6 (depends on 5) A method as claimed in claim 5, wherein said at least one local interconnect conductor has a length L and a width W, both measured in a plane substantially parallel to said substrate, L being at least three times larger than W. ### Claim 7 (depends on 1) A method as claimed in claim 1, wherein said gate electrode is formed of polysilicon. ### Claim 8 (depends on 1) A method as claimed in claim 1, wherein said at least one local interconnect conductor is formed of tungsten. ### Claim 9 (depends on 1) A method as claimed in claim 1, wherein said at least one local interconnect conductor and said gate electrode are formed in respective openings in a lower insulator layer. ### Claim 10 (depends on 9) A method as claimed in claim 9, comprising the step of forming an etch stop layer so as at least to cover said lower insulator layer surrounding where said gate opening is to be etched and not to cover said upper surface of said gate electrode and wherein etching of said gate opening does not etch through said etch stop layer. ### Claim 11 (depends on 10) A method as claimed in claim 10, wherein said etch stop layer is formed to cover said upper surface of said at least one local interconnect conductor and etching of said electrode opening does etch through said etch stop layer and is performed in a separate step to etching said gate opening. ### Claim 12 (depends on 1) A method as claimed in claim 1, wherein said etching of said at least one electrode source opening is performed in a separate etching step to etching of said gate opening and etching of said gate opening is performed with etching parameters selected to etch to a depth insufficient to reach said diffusion layer. ### Claim 13 (depends on 12) A method as claimed in claim 12, wherein said gate opening is covered by a resist layer during etching of said at least one electrode opening. ### Claim 14 (depends on 1) A method as claimed in claim 1, wherein said etching of said at least one electrode opening and said gate opening are performed in a common etching step with etching parameters selected to etch to a depth insufficient to reach said diffusion layer. ### Claim 15 (depends on 1) A method as claimed in claim 1, comprising the steps of forming an etch stop layer so as at least to cover said substrate surrounding said gate electrode and said gate electrode and removing said etch stop layer from said upper surface of said gate electrode and wherein etching of said gate opening does not etch through said etch stop layer. ### Claim 16 (depends on 1) A method as claimed in claim 1, comprising a step of depositing a first metal connection layer over said at least one electrode connection conductor and said gate connection conductor so as to connect a transistor comprising said diffusion layer, said gate electrode and said at least one local interconnect conductor to other portions of said integrated circuit. ### Claim 17 (depends on 16) A method as claimed in claim 16, wherein said first metal connection layer is a dual damascene layer formed with said at least one electrode connection conductor and said gate connection conductor. ### Claim 18 (depends on 16) A method as claimed in claim 16, wherein said first metal layer is formed of rectilinear conductors disposed substantially perpendicular to a major axis of said at least one local interconnect conductor and said gate electrode. ### Claim 19 (depends on 1) A method as claimed in claim 1, wherein said integrated circuit is formed of a plurality of circuit cells and a majority of said plurality of circuit cells are formed by depositing components having all pure rectilinear shapes. ### Claim 20 (depends on 1) A method as claimed in claim 1, wherein at least one of said at least one local interconnect conductor connects a transistor comprising said diffusion layer, said gate electrode and said at least one local interconnect conductor to other portions of said integrated circuit. ### Claim 21 An integrated circuit comprising: a diffusion region formed on a semiconductor substrate; at least one local interconnect conductor formed on said diffusion region, each local interconnect conductor respectively forming one of a source electrode and a drain electrode; a gate electrode formed on said diffusion region, said gate electrode being spaced by a gate insulator layer from said diffusion region, said at least one local interconnect conductor extending above the diffusion region a distance comparable to a distance said gate electrode extends above the diffusion region; an insulator layer formed over said diffusion region and having at least one electrode opening reaching at least an upper surface of said at least one local interconnect conductor and a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, said gate opening having a maximum depth insufficient to reach said diffusion region; an electrode connection conductor deposited in said at least one electrode opening; and a gate connection conductor deposited in said gate opening. ### Claim 22 (depends on 21) An integrated circuit as claimed in claim 21, wherein said at least one local interconnect conductor comprises a drain local interconnect conductor and a source local interconnect conductor, a drain opening reaching to an upper surface of said drain local interconnect conductor and a source opening reaching to an upper surface of said source local interconnect conductor. ### Claim 23 (depends on 22) An integrated circuit as claimed in claim 22, wherein said gate electrode is disposed on said diffusion region between said source local interconnect conductor and said drain local interconnect conductor. ### Claim 24 (depends on 21) An integrated circuit as claimed in claim 21, wherein said one or more electrode openings overlie said diffusion region. ### Claim 25 (depends on 21) An integrated circuit as claimed in claim 21, wherein said at least one local interconnect conductor and said gate electrode are substantially parallel rectilinear bodies. ### Claim 26 (depends on 25) An integrated circuit as claimed in claim 25, wherein said at least one local interconnect conductor has a length L and a width W, both measured in a plane substantially parallel to said substrate, L being at least three times larger than W. ### Claim 27 (depends on 21) An integrated circuit as claimed in claim 21, wherein said gate electrode is formed of polysilicon. ### Claim 28 (depends on 21) An integrated circuit as claimed in claim 21, wherein said at least one local interconnect conductor is formed of tungsten. ### Claim 29 (depends on 21) An integrated circuit as claimed in claim 21, wherein said at least one local interconnect conductor and said gate electrode are formed in respective openings in a lower insulator layer. ### Claim 30 (depends on 29) An integrated circuit as claimed in claim 29, comprising an etch stop layer at least covering said lower insulator layer surrounding said gate opening and not covering said upper surface of said gate electrode. ### Claim 31 (depends on 21) An integrated circuit as claimed in claim 21, comprising an etch stop layer covering said substrate surrounding said gate electrode and side walls of said gate electrode and not covering said upper surface of said gate electrode. ### Claim 32 (depends on 21) An integrated circuit as claimed in claim 21, comprising a first metal connection layer deposited over said at least one electrode connection conductor and said gate connection conductor so as to connect a transistor comprising said diffusion layer, said gate electrode and said at least one local interconnect conductor to other portions of said integrated circuit. ### Claim 33 (depends on 32) An integrated circuit as claimed in claim 32, wherein said first metal connection layer is a dual damascene layer formed with said at least one electrode connection conductor and said gate connection conductor. ### Claim 34 (depends on 32) An integrated circuit as claimed in claim 32, wherein said first metal layer comprises rectilinear conductors disposed substantially perpendicular to a major axis of said at least one local interconnect conductor and said gate electrode. ### Claim 35 (depends on 21) An integrated circuit as claimed in claim 21, wherein said integrated circuit is formed of a plurality of circuit cells and a majority of said plurality of circuit cells are formed by depositing components having all pure rectilinear shapes. ### Claim 36 (depends on 21) An integrated circuit as claimed in claim 21, wherein at least one of said at least one local interconnect conductors connects a transistor comprising said diffusion layer, said gate electrode and said at least one local interconnect conductor to other portions of said integrated circuit. ### Claim 37 A method of making an integrated circuit, said method comprising the steps of: forming on a diffusion region of a semiconductor substrate a gate electrode spaced by a gate insulator layer from said diffusion region; depositing an insulator layer over said diffusion region and said gate electrode; in separate etching steps using separate patterns formed on said insulator layer etching through said insulator layer at least one electrode opening reaching an upper surface of diffusion region for forming an electrode and etching a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, etching of said gate opening being such that said gate opening has a maximum depth insufficient to reach said diffusion region; and depositing an electrode connection conductor in said at least one electrode opening and a gate connection conductor in said gate opening. ### Claim 38 (depends on 37) A method as claimed in claim 37, wherein said at least electrode opening comprises a source opening and a drain opening for forming a source electrode and a drain electrode. ### Claim 39 (depends on 37) A method as claimed in claim 37, wherein said one or more electrode openings overlie said diffusion region. ### Claim 40 (depends on 38) A method as claimed in claim 38, wherein said source electrode, said drain electrode and said gate electrode are substantially parallel rectilinear bodies. ### Claim 41 (depends on 37) A method as claimed in claim 37, wherein said electrode has a length L and a width W, both measured in a plane substantially parallel to said substrate, L being at least three times larger than W. ### Claim 42 (depends on 37) A method as claimed in claim 37, wherein said gate electrode is formed of polysilicon. ### Claim 43 (depends on 37) A method as claimed in claim 37, wherein said at least one electrode is formed of tungsten. ### Claim 44 (depends on 37) A method as claimed in claim 37, wherein said gate opening is covered by a resist layer during etching of said at least one electrode opening. ### Claim 45 (depends on 37) A method as claimed in claim 37, comprising the steps of forming an etch stop layer so as at least to cover said substrate surrounding said gate electrode and said gate electrode and removing said etch stop layer from said upper surface of said gate electrode and wherein etching of said gate opening does not etch through said etch stop layer. ### Claim 46 (depends on 37) A method as claimed in claim 37, comprising a step of depositing a first metal connection layer over said at least one electrode connection conductor and said gate connection conductor so as to connect a transistor comprising said diffusion layer, said gate electrode and said at least one electrode to other portions of said integrated circuit. ### Claim 47 (depends on 46) A method as claimed in claim 46, wherein said first metal connection layer is a dual damascene layer formed with said at least one electrode connection conductor and said gate connection conductor. ### Claim 48 (depends on 46) A method as claimed in claim 46, wherein said first metal layer is formed of rectilinear conductors disposed substantially perpendicular to a major axis of said gate electrode. ### Claim 49 (depends on 37) A method as claimed in claim 37, wherein said integrated circuit is formed of a plurality of circuit cells and a majority of said plurality of circuit cells are formed by depositing components having all pure rectilinear shapes. ### Claim 50 An integrated circuit comprising: a diffusion region formed on a semiconductor substrate; a gate electrode formed on said diffusion region, said gate electrode being spaced by a gate insulator layer from said diffusion region; an insulator layer formed over said diffusion region and having at least one electrode opening reaching at least an upper surface of said diffusion region and a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, said gate opening having a maximum depth insufficient to reach said diffusion region; an electrode connection conductor deposited in said at least one electrode opening; and a gate connection conductor deposited in said gate opening.