# US 7,745,264 B2 · Semiconductor chip with stratified underfill > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,745,264 B2 - Document ID: US7745264B2 - Status: Granted - Kind: B2 - Application number: 11/849,545 - Filed: 2007-09-04 - Published: 2009-03-05 - Granted: 2010-06-29 - Earliest claimed: 2007-09-04 - Assignees: Advanced Micro Devices, Inc. - Inventors: Jun Zhai; Ranjit Gannamani; Srinivasan Parthasarathy - Web page: https://patentgrep.com/patent/US7745264B2 ## CPC - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/144: {the encapsulations comprising foils} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 76/15: Containers comprising an insulating or insulated base - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/90: Bond pads, in general - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip. ## Claims ### Claim 1 A method of manufacturing, comprising: coupling a semiconductor chip to a substrate to leave a gap therebetween; and forming an underfill layer in the gap, the underfill layer including a first plurality of filler particles having a first average density and a second plurality of filler particles having a second average density lower than the first average density such that the first plurality of filler particles being concentrated proximate the substrate and the second plurality of filler particles being concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer being larger proximate the substrate than proximate the semiconductor chip. ### Claim 2 (depends on 1) The method of claim 1, wherein the forming the underfill layer comprises depositing a polymeric resin and wherein the first plurality of filler particles comprises alumina and the second plurality of filler particles comprise silica. ### Claim 3 (depends on 1) The method of claim 1, wherein the forming the underfill layer comprises depositing a polymeric resin and wherein the first and second pluralities of filler particles comprise round particles. ### Claim 4 (depends on 1) The method of claim 1, wherein the coupling a semiconductor chip comprises coupling a microprocessor. ### Claim 5 A method of manufacturing, comprising: forming a partially cured polymeric material layer having first bulk modulus on a surface of a semiconductor chip; coupling the semiconductor chip to a substrate with the partially cured polymeric material facing towards the substrate to leave a gap therebetween; and forming an underfill layer in the gap between the partially cured polymeric material, the underfill layer including a plurality of filler particles providing the underfill layer with a second bulk modulus larger than the first bulk modulus of the partially cured polymeric material layer. ### Claim 6 (depends on 5) The method of claim 5, wherein the forming the underfill layer comprises depositing a polymeric resin and wherein the plurality of filler particles comprises alumina, silica, diamond or sapphire. ### Claim 7 (depends on 5) The method of claim 5, wherein the forming the underfill layer comprises depositing a polymeric resin and wherein the plurality of filler particles comprises round particles. ### Claim 8 (depends on 5) The method of claim 5, wherein the coupling a semiconductor chip comprises coupling a microprocessor. ### Claim 9 An apparatus, comprising: a semiconductor chip coupled to a substrate; and an underfill layer between the semiconductor chip and the substrate, the underfill layer including a first plurality of filler particles having a first average density and a second plurality of filler particles having a second average density lower than the first average density such that the first plurality of filler particles being concentrated proximate the substrate and the second plurality of filler particles being concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer being larger proximate the substrate than proximate the semiconductor chip. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the underfill layer comprises a polymeric resin and wherein the first plurality of filler particles comprises alumina and the second plurality of filler particles comprises silica. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the underfill layer comprises a polymeric resin and wherein the first and second pluralities of filler particles comprise round particles. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the semiconductor chip comprises a microprocessor. ### Claim 13 An apparatus, comprising: forming a partially cured polymeric material layer having first bulk modulus on a surface of a semiconductor chip; semiconductor chip coupled to a substrate; and an underfill layer between the semiconductor chip and the substrate, the underfill layer having a first layer proximate the semiconductor chip and having a first bulk modulus, and a second layer proximate the substrate including a plurality of filler particles providing the second layer with a second bulk modulus larger than the first bulk modulus of the first layer. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the second layer comprises a polymeric resin and wherein the plurality of filler particles comprises alumina, silica, diamond or sapphire. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the semiconductor chip comprises a microprocessor. ### Claim 16 A method of manufacturing, comprising: coupling a semiconductor chip to a substrate to leave a gap therebetween; and forming an underfill layer in the gap, the underfill layer including a first portion proximate the substrate that has a first coefficient of thermal expansion and a majority concentration of first filler particles with a first average size, and a second portion proximate the semiconductor chip that has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion and a majority concentration of second filler particles with a second average size smaller than the first average size. ### Claim 17 (depends on 16) The method of claim 16, wherein the forming the underfill layer comprises depositing a polymeric resin and wherein the first and second filler particles comprise silica particles. ### Claim 18 (depends on 16) The method of claim 16, wherein the forming the underfill layer comprises depositing a polymeric resin and wherein the first and second filler particles comprise round particles. ### Claim 19 (depends on 16) The method of claim 16, wherein the coupling a semiconductor chip comprises coupling a microprocessor. ### Claim 20 An apparatus, comprising: a semiconductor chip coupled to a substrate; and an underfill layer between the semiconductor chip and the substrate, the underfill layer including a first portion proximate the substrate that has a first coefficient of thermal expansion and a majority concentration of first filler particles with a first average size, and a second portion proximate the semiconductor chip that has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion and a majority concentration of second filler particles with a second average size smaller than the first average size. ### Claim 21 (depends on 20) The apparatus of claim 20, wherein the underfill layer comprises a polymeric resin and wherein the first and second filler particles comprise silica particles. ### Claim 22 (depends on 20) The apparatus of claim 20, wherein the underfill layer comprises a polymeric resin and wherein the first and second filler particles comprise round particles. ### Claim 23 (depends on 20) The apparatus of claim 20, wherein the semiconductor chip comprises a microprocessor.