# US 7,745,260 B2 · Method of forming semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,745,260 B2 - Document ID: US7745260B2 - Status: Granted - Kind: B2 - Application number: 12/234,709 - Filed: 2008-09-22 - Published: 2010-03-25 - Granted: 2010-06-29 - Earliest claimed: 2008-09-22 - Assignees: Freescale Semiconductor, Inc. - Inventors: Wai Yew Lo - Web page: https://patentgrep.com/patent/US7745260B2 ## CPC - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/114: {by a substrate and the encapsulations} - H10W 72/0198: {batch processes} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming a semiconductor package (10) including forming a plurality of cavities (14) in a substrate (12). An electrically conductive pattern (16) is formed on the substrate (12) and over the cavities (14). An electrically insulating layer (22) is formed over the substrate (12) and the electrically conductive pattern (16). A plurality of vias (24) is formed in the electrically insulating layer (22). An integrated circuit (IC) die (28) is attached to the electrically insulating layer (22) and electrically connected to the vias (24) such that the IC die (28) is connected to the electrically conductive pattern (16). A molding operation is performed to encapsulate the IC die (28). The substrate (12) is removed such that the electrically conductive pattern (16) is exposed. ## Claims ### Claim 1 A method of forming a semiconductor package, comprising: forming a plurality of cavities in a substrate; forming an electrically conductive pattern on the substrate and over the cavities; forming an electrically insulating layer over the substrate and the electrically conductive pattern; forming a plurality of vias in the electrically insulating layer; attaching an integrated circuit (IC) die to the electrically insulating layer; electrically connecting the IC die to the vias, thereby connecting the IC die to the electrically conductive pattern; performing a molding operation to encapsulate the IC die; and removing the substrate, thereby exposing the electrically conductive pattern. ### Claim 2 (depends on 1) The method of forming a semiconductor package according to claim 1, wherein the cavities are formed in the substrate in accordance with a predetermined land pattern for the semiconductor package. ### Claim 3 (depends on 1) The method of forming a semiconductor package according to claim 1, wherein the cavities are formed in a full area array layout on the substrate. ### Claim 4 (depends on 1) The method of forming a semiconductor package according to claim 1, wherein the electrically conductive pattern comprises a plurality of traces and a plurality of conductive bumps, each of the conductive bumps corresponding to respective ones of the cavities. ### Claim 5 (depends on 4) The method of forming a semiconductor package according to claim 4, wherein a portion of the traces extends between respective ones of the vias and respective ones of the conductive bumps located on a central portion of the semiconductor package. ### Claim 6 (depends on 4) The method of forming a semiconductor package according to claim 4, further comprising forming a second electrically insulating layer over the exposed traces. ### Claim 7 (depends on 1) The method of forming a semiconductor package according to claim 1, wherein the step of forming the vias in the electrically insulating layer comprises: forming a plurality of through-holes through the electrically insulating layer to the electrically conductive pattern. ### Claim 8 (depends on 7) The method of forming a semiconductor package according to claim 7, wherein the step of forming the vias in the electrically insulating layer further comprises: plating the through-holes with an electrically conductive material. ### Claim 9 (depends on 1) The method of forming a semiconductor package according to claim 1, wherein the electrically insulating layer comprises a solder resist layer. ### Claim 10 (depends on 1) The method of forming a semiconductor package according to claim 1, wherein the substrate comprises an electrically conductive material. ### Claim 11 A method of forming a plurality of semiconductor packages, comprising: forming a plurality of cavities in a substrate; forming an electrically conductive pattern on the substrate and atop the cavities; forming an electrically insulating layer over the substrate and the electrically conductive pattern; forming a plurality of vias in the electrically insulating layer; attaching a plurality of integrated circuit (IC) dice to the electrically insulating layer; electrically connecting the IC dice to the vias, thereby connecting the IC dice to the electrically conductive pattern; performing a molding operation to encapsulate the IC dice; and removing the substrate, thereby exposing the electrically conductive pattern. ### Claim 12 (depends on 11) The method of forming a plurality of semiconductor packages according to claim 11, wherein the cavities are formed in the substrate in accordance with a predetermined land pattern for the semiconductor packages. ### Claim 13 (depends on 11) The method of forming a plurality of semiconductor packages according to claim 11, wherein the electrically conductive pattern comprises a plurality of traces and a plurality of conductive bumps, each of the conductive bumps corresponding to respective ones of the cavities. ### Claim 14 (depends on 11) The method of forming a plurality of semiconductor packages according to claim 11, wherein the step of forming the vias in the electrically insulating layer comprises: forming a plurality of through-holes through the electrically insulating layer to the electrically conductive pattern. ### Claim 15 (depends on 14) The method of forming a plurality of semiconductor packages according to claim 14, wherein the step of forming the vias in the electrically insulating layer further comprises: plating the through-holes with an electrically conductive material. ### Claim 16 A method of forming a semiconductor package, comprising: forming a plurality of cavities in a substrate; forming an electrically conductive pattern on the substrate and over the cavities; forming an electrically insulating layer over the substrate and the electrically conductive pattern; forming a plurality of through-holes through the electrically insulating layer to the electrically conductive pattern; plating the through-holes with an electrically conductive material to form a plurality of vias in the electrically insulating layer; attaching an integrated circuit (IC) die to the electrically insulating layer; electrically connecting the IC die to the vias with a plurality of bonding wires, thereby connecting the IC die to the electrically conductive pattern; performing a molding operation to encapsulate the IC die and the bonding wires; and removing the substrate, thereby exposing the electrically conductive pattern. ### Claim 17 (depends on 16) The method of forming a semiconductor package according to claim 16, wherein the cavities are formed in the substrate in accordance with a predetermined land pattern for the semiconductor package. ### Claim 18 (depends on 16) The method of forming a semiconductor package according to claim 16, wherein the cavities are formed in a full area array layout on the substrate. ### Claim 19 (depends on 16) The method of forming a semiconductor package according to claim 16, wherein the electrically conductive pattern comprises a plurality of traces and a plurality of conductive bumps, each of the conductive bumps corresponding to respective ones of the cavities. ### Claim 20 (depends on 19) The method of forming a semiconductor package according to claim 19, wherein a portion of the traces extends between respective ones of the vias and respective ones of the conductive bumps located on a central portion of the semiconductor package.