# US 7,745,255 B2 · Bonding pad structure, electronic device having a bonding pad structure and methods of fabricating the same

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- Number: US 7,745,255 B2
- Document ID: US7745255B2
- Status: Granted
- Kind: B2
- Application number: 12/010,807
- Filed: 2008-01-30
- Published: 2008-08-21
- Granted: 2010-06-29
- Earliest claimed: 2007-02-16
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jae-Hyun Lee; Hyung-Moo Park
- Web page: https://patentgrep.com/patent/US7745255B2

## CPC

- H10W 72/019: {of bond pads}
- H10W 72/075: {of bond wires}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

## Claims

### Claim 1

A method of fabricating an electronic device having a bonding pad structure, comprising:
forming a first bonding pad on a substrate;
forming a second bonding pad spaced apart from the first bonding pad, wherein a top surface of the second bonding pad is formed at a higher level than the first bonding pad,
wherein the bonding pad structure includes at least two first bonding pads and at least two second bonding pads;
forming a lower insulating layer on the substrate, wherein the first bonding pads pass through the lower insulating layer;
forming an upper insulating layer on a portion of the substrate having the first bonding pads, wherein the second bonding pads sequentially pass through the upper insulating layer and the lower insulating layer; and
exposing top surfaces of the first bonding pads by etching the upper insulating layer using the second bonding pads as etching masks.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first bonding pads are formed covering a portion of a top surface of the lower insulating layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the second bonding pads are formed covering a portion of a top surface of the upper insulating layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the forming of the first bonding pads includes:
forming first pad holes passing through the lower insulating layer by patterning the lower insulating layer;
forming a first pad layer on a portion the substrate having the first pad holes; and
patterning the first pad layer.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising:
forming a first buffer layer on the first pad, after forming the first pad layer;
forming first buffer patterns on the first bonding pads by patterning the first buffer layer while patterning the first pad layer;
etching the upper insulating layer using the second bonding pads as an etching mask; and
removing the first buffer patterns.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the second bonding pads includes:
forming second pad holes passing though the upper insulating layer and the lower insulating layer by patterning the upper insulating layer and the lower insulating layer;
forming a second pad layer on the substrate with the second pad holes; and
patterning the second pad layer.

### Claim 7 (depends on 6)

The method according to claim 6, further comprising:
forming a second buffer layer on the second pad layer, after forming the second pad layer;
forming second buffer patterns on the second bonding pads by patterning the second buffer layer while patterning the second pad layer;
etching the upper insulating layer; and
removing the second buffer patterns.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
forming a spacer insulating layer on a portion of the substrate having top surfaces of the first bonding pads exposed and the second bonding pads; and
forming insulating spacers on side walls of the second bonding pads by anisotropically etching the spacer insulating layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the insulating spacers cover the side walls of the second bonding pads and a portion of the first bonding pads.

### Claim 10 (depends on 1)

The method according to claim 1, further comprising:
forming insulating spacers on the side walls of the second bonding pads after forming the second bonding pads.