# US 7,745,247 B2 · Solid-state image sensor and imaging system

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- Number: US 7,745,247 B2
- Document ID: US7745247B2
- Status: Granted
- Kind: B2
- Application number: 12/250,282
- Filed: 2008-10-13
- Published: 2009-04-23
- Granted: 2010-06-29
- Earliest claimed: 2004-09-03
- Assignees: Canon Kabushiki Kaisha
- Inventors: Toru Koizumi; Akira Okita; Tetsuya Itano; Sakae Hashimoto; Ryuichi Mishima
- Web page: https://patentgrep.com/patent/US7745247B2

## CPC

- H10F 39/811: {Interconnections}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/805: {Coatings}
- H10F 39/8053: {Colour filters}
- H10F 39/806: {Optical elements or arrangements associated with the image sensors}
- H10F 39/8063: {Microlenses}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.

## Claims

### Claim 1

A method of formation of a solid state image sensor comprising:
forming at least one source-drain region of MOS transistors;
forming a first layer on the at least one source drain region;
forming a plurality of insulating layers and a plurality of wiring layers, wherein the wiring layer furthest from the first layer is referred to as the outer wiring layer;
planarizing at least one of the insulating layers;
forming a plasma CVD layer above the outer wiring layer;
heating the plasma CVD layer at a target temperature in a target environment for a target period of time; and
forming an optical element on the plasma CVD layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first layer is made of SiO2.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the first layer is planarized by a CMP process.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the outer wiring layer is connected to a power supply.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the plasma CVD layer is made of SiN and has a thickness of about 600 nm.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the target temperature is between 390° C.-470° C. with a target period of time of about 120 minutes in a target environment including hydrogen.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the at least one of the insulating layers is planarized by a CMP process.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
forming a second layer having higher refractive index than that of the first layer on and in contact with the first layer.

### Claim 9 (depends on 2)

The method according to claim 2, further comprising before forming the plasma CVD layer:
forming a second layer, above the outer wiring layer, having higher refractive index than that of the insulating layer disposed under the outer wiring layer.

### Claim 10 (depends on 2)

The method according to claim 2, further comprising before forming the plasma CVD layer:
forming a second layer having higher refractive index than that of the insulating layer disposed so as to cover the outer wiring layer.