# US 7,745,244 B2 · Pin substrate and package

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- Number: US 7,745,244 B2
- Document ID: US7745244B2
- Status: Granted
- Kind: B2
- Application number: 12/144,289
- Filed: 2008-06-23
- Published: 2009-12-24
- Granted: 2010-06-29
- Earliest claimed: 2008-06-23
- Assignees: Fairchild Semiconductor Corporation
- Inventors: Zhongfa Yuan; Yong Liu; Yumin Liu; Qiuxiao Qian
- Web page: https://patentgrep.com/patent/US7745244B2

## CPC

- H10W 70/635: {Through-vias}
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H10W 70/095: {of vias therein}
- H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components}
- H05K 2201/10287: Metal wires as connectors or conductors
- H05K 2201/10378: Interposers
- H05K 2203/0235: Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
- H10W 72/0198: {batch processes}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49158: with molding of insulated base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

## Claims

### Claim 1

A method of forming a substrate for use in a semiconductor package, the method comprising:
inserting a plurality of conductive wires into an alignment fixture;
placing at least a portion of the plurality of conductive wires and at least a portion of the alignment fixture in a mold, wherein the mold is separate from the alignment fixture;
filling the mold with a molding compound;
curing the molding compound to create a pre-substrate block; and
cutting the pre-substrate block, wherein cutting the pre-substrate block comprises cutting the plurality of conductive wires.

### Claim 2 (depends on 1)

The method of claim 1 wherein the mold is in the shape of a square cylinder.

### Claim 3 (depends on 1)

The method of claim 1 wherein the mold is in the shape of a round cylinder.

### Claim 4 (depends on 1)

The method of claim 1 wherein the molding compound comprises an epoxy molding compound.

### Claim 5 (depends on 1)

The method of claim 1 wherein each wire in the plurality of conductive wires includes a first end surface and a second end surface, and the molding compound comprises a first and second surface after cutting the pre-substrate block, further wherein the second surface of the molding compound is substantially co-planar with the second end surface of each wire in the plurality of conductive wires, and the first surface of the molding compound is substantially co-planar with the first end surface of each wire in the plurality of conductive wires.

### Claim 6 (depends on 1)

The method of claim 1 wherein each wire in the plurality of conductive wires comprises copper.

### Claim 7 (depends on 1)

The method of claim 1 wherein each wire in the plurality of conductive wires comprises gold.

### Claim 8 (depends on 6)

The method of claim 6, wherein each wire in the plurality of conductive wires comprises a solid conducting material.

### Claim 9 (depends on 7)

The method of claim 7, wherein each wire in the plurality of conductive wires comprises a solid conducting material.

### Claim 10 (depends on 1)

The method of claim 1, wherein the alignment fixture includes a top plate having holes and a bottom plate having holes.

### Claim 11

A method of forming a substrate for use in a semiconductor package, the method comprising:
placing a plurality of conductive wires in a mold, wherein the placing a plurality of conductive wires in a mold includes placing the plurality of conductive wires within an alignment fixture, wherein the alignment fixture includes a top plate having holes and a bottom plate having holes, wherein the mold includes a slot, the method further comprising putting the top plate within the slot;
filling the mold with a molding compound;
curing the molding compound to create a pre-substrate block; and
cutting the pre-substrate block.

### Claim 12 (depends on 10)

The method of claim 10, wherein the placing the at least a portion of the plurality of conductive wires within the alignment fixture comprises:
inserting top portions of the plurality of conductive wires into the holes in the top plate;
inserting bottom portions of the plurality of conductive wires into the holes in the bottom plate;
melting the bottom portions of the plurality of conductive wires to form flash balls; and
moving the top plate and the bottom plate outward.

### Claim 13 (depends on 10)

The method of claim 10, wherein the top plate has a top plate inner side, and the bottom plate has a bottom plate inner side, further wherein both the top plate inner side and the bottom plate inner side are coated with a release layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein the top plate and the bottom plate are slidably coupled to one or more guides.

### Claim 15 (depends on 14)

The method of claim 14, wherein the top plate is a first top plate, the method further comprising:
bending the top portions of the plurality of conductive wires;
attaching a second top plate to the one or more guides;
moving the second top plate inwards to clamp the bent top portions of the plurality of conductive wires against the first top plate.