# US 7,744,182 B2 · Capacitive load driving circuit and method, and liquid drop ejecting device

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- Number: US 7,744,182 B2
- Document ID: US7744182B2
- Status: Granted
- Kind: B2
- Application number: 11/438,170
- Filed: 2006-05-22
- Published: 2007-04-05
- Granted: 2010-06-29
- Earliest claimed: 2005-10-05
- Assignees: Fuji Xerox Co., Ltd.
- Inventors: Kota Nakayama
- Web page: https://patentgrep.com/patent/US7744182B2

## CPC

- B41J 2/04588: {using a specific waveform}
- B41J 2/04541: {Specific driving circuit}
- B41J 2/04548: {Details of power line section of control circuit}
- B41J 2/04581: {controlling heads based on piezoelectric elements}
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS

## Abstract

A capacitive load driving circuit that supplies driving voltage to a capacitive load includes a driving voltage waveform generating unit. The driving voltage waveform generating unit, at times of charging or discharging of the capacitive load, generates a driving voltage waveform in which potential applied to the capacitive load varies stepwise from a first potential to a second potential during a predetermined time period.

## Claims

### Claim 1

A capacitive load driving circuit supplying driving voltage to a capacitive load, the circuit comprising:
a driving voltage waveform generating unit which, at times of charging or discharging of the capacitive load, generates a driving voltage waveform in which potential applied to the capacitive load varies stepwise from a first potential to a second potential during a predetermined time period;
wherein the driving voltage waveform generating unit has a plurality of power sources providing a plurality of potentials from the first potential to the second potential, and a plurality of switching elements switching supply to the capacitive load of the potentials provided by the plurality of power sources, the plurality of switching elements carrying out switching operation such that the potential applied to the capacitive load varies stepwise from the first potential to the second potential,
wherein one end of the capacitive load is connected to a reference potential and the other end of the capacitive load is connected to the plurality of power sources providing different potentials respectively via the plurality of switching elements, and
wherein the plurality of power sources includes a first power source that provides the first potential with respect to the reference potential, a second power source that provides the second potential with respect to the reference potential, and at least a third power source that provides an intermediate potential between the first potential and the second potential with respect to the reference potential, and the plurality of power sources are constant power sources that provide constant potentials,
wherein a driving voltage waveform in which potential applied to the capacitive load varies stepwise at least three steps during charging and during discharging, and the differences in potentials for each adjacent steps are even.

### Claim 2 (depends on 1)

The capacitive load driving circuit of claim 1, wherein the driving voltage waveform includes a portion which varies continuously on the basis of a time constant which is determined by the capacitive load and at least one portion of a driving circuit.

### Claim 3 (depends on 1)

The capacitive load driving circuit of claim 1, wherein the predetermined time period is a time period which is set on the basis of a time constant which is determined by the capacitive load and at least one portion of a driving circuit.

### Claim 4 (depends on 1)

The capacitive load driving circuit of claim 1, wherein the capacitive load includes a piezoelectric element.

### Claim 5 (depends on 1)

The capacitive load driving circuit of claim 1, wherein a plurality of power sources are provided as the third power source.

### Claim 6 (depends on 1)

The capacitive load driving circuit of claim 1, wherein the plurality of switching elements include first and second PMOS transistors and an NMOS transistor, the source of the NMOS transistor is connected to the reference potential, the source of the first PMOS transistor is connected to the second power source, the source of the second PMOS transistor is connected to the third power source, and the drains of the first and second PMOS transistors are both connected to the drain of the NMOS transistor and said other end of the capacitive load.

### Claim 7

A liquid drop ejecting device comprising:
a liquid drop ejecting head having a nozzle, a pressure generating chamber in which liquid drops to be ejected from the nozzle are filled, and a capacitive load provided in correspondence with the pressure generating chamber, the liquid drop ejecting head ejecting a liquid drop from the nozzle by applying voltage corresponding to a driving signal to the capacitive load and changing a volume of the pressure generating chamber; and
a capacitive load driving circuit supplying driving voltage to the capacitive load, and having a driving voltage waveform generating unit which, at times of charging or discharging of the capacitive load, generates a driving voltage waveform in which potential applied to the capacitive load varies stepwise from a first potential to a second potential during a predetermined time period;
wherein the driving voltage waveform generating unit has a plurality of power sources supplying a plurality of potentials from the first potential to the second potential, and a plurality of switching elements switching supply to the capacitive load of the potentials supplied by the plurality of power sources, the plurality of switching elements carrying out switching operation such that the potential applied to the capacitive load varies stepwise from the first potential to the second potential,
wherein one end of the capacitive load is connected to a reference potential and the other end of the capacitive load is connected to the plurality of power sources providing different potentials respectively via the plurality of switching elements, and wherein the plurality of power sources includes a first power source that provides the first potential with respect to the reference potential, a second power source that provides the second potential with respect to the reference potential, and at least a third power source that provides an intermediate potential between the first potential and the second potential with respect to the reference potential, and the plurality of power sources are constant power sources that provide constant potentials,
wherein a driving voltage waveform in which potential applied to the capacitive load varies stepwise at least three steps during charging and during discharging, and the differences in potentials for each adjacent steps are even.

### Claim 8 (depends on 7)

The liquid drop ejecting device of claim 7, wherein the driving voltage waveform includes a portion which varies continuously on the basis of a time constant which is determined by the capacitive load and at least one portion of a driving circuit.

### Claim 9 (depends on 7)

The liquid drop ejecting device of claim 7, wherein the predetermined time period is a time period which is set on the basis of a time constant which is determined by the capacitive load and at least one portion of a driving circuit.

### Claim 10 (depends on 7)

The liquid drop ejecting device of claim 7, wherein the capacitive load includes a piezoelectric element.

### Claim 11 (depends on 7)

The liquid drop ejecting device of claim 7, wherein a plurality of power sources are provided as the third power source.

### Claim 12 (depends on 7)

The liquid drop ejecting device of claim 7, wherein the plurality of switching elements include first and second PMOS transistors and an NMOS transistor, the source of the NMOS transistor is connected to the reference potential, the source of the first PMOS transistor is connected to the second power source, the source of the second PMOS transistor is connected to the third power source, and the drains of the first and second PMOS transistors are both connected to the drain of the NMOS transistor and said other end of the capacitive load.